[SI-LIST] Time step resoution in Hspice
- From: "Sogo Hsu" <sogo.hsu@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 12 Oct 2004 03:40:28 -0000
Hi Gurus,
As digital signal speed does keep getting faster, the difficulty of
meeting jitter requirement is more rigorous. Recently, we tried to
characterize jitter mechanism for SERDES. First of all, we conducted
a simple scenario for observation of signals transmitting through T-
line element. The sp file is shown as below.
=======================================================
.option accurate
.option converge=1 gmindc=1.0000e-15
Vgp5 nd_in11 0 PWL 0N 0.5V, 0.39N 0.5V, 0.4N -0.5V, 0.79N -0.5V,
0.8N 0.5V, R 0N
Rin1 nd_in11 nd_in11t 50
Tbreakout nd_in11t 0 out_p 0 Z0=50 Td=1ns
Rt1 out_p 0 50
*Analysis
.tran 100ps 1us start=0ns
.option post probe
.probe PAR('v(out_p)')
.probe PAR('v(nd_in11)')
.END
=====================================================
The voltage source is a clock signal switching between -0.5V to 0.5V
with 1.25GHz frequency. Theorectically, results of Vout should be
the same as the source signal. But, it seems that the cycle width of
signals at Vout is not always to be 800ps. At time point near 200ns,
its value is 800.0001ps. While at 600ns, its value is 800.0143ps.
And at 800ns, the value is 799.9574ps.
We don't realize why this difference occurs. Does there any method
to increase the precision of simulation result to eliminate this
difference? Or something wrong in the spice circuit linkage? The
little turbulence in time will affact the characterization of
jitter. Besides, there seems to be a overshoot about 8mV at the
rising edge of signals at Vout.
Thanks in advance!
Sogo Hsu, Ph. D.
Simulation center/Foxconn
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