[SI-LIST] Re: Test PCB structures
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: <janton@xxxxxxxxxxxxx>, "Si-List" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 5 Jan 2006 07:30:58 -0800
I'm surprised at the dirth of responses - folks keeping stuff "close to
their chest", or still on vacation?
I would encourage you to use on-board TRL, as well as the SOLT
structures someone else suggested. This basically means adding the
appropriate "Lines" for your frequencies of interest to the Short (or
Open) and Thru. Having the Short, Open, and Thru will also be
sufficient for TDR cal.
Stuff I can remember (out of a seemingly infinite list of "gotchas"):
1) Use a well-thought out trace naming convention. On one board,
we used "1tx_p_a", for instance, where:
a. "1" is the topology number (in this case, 1 was the
reference - the simplest trace)
b. "t" indicated it was routed on the top layer, vs.
stripline or bottom
c. "x" indicated it was the shortest length, vs. "y"
(medium), or "z" (longest)
d. "p" indicated the positive half of a differential pair
(assignment of positive vs. negative being arbitrary)
e. "a" indicated this was the left-hand side of the trace.
The trace would end at the "b" side.
Having a similar naming convention will allow you to put all relevant
information on filenames of traces that you capture, without excessive
characters in that filename. If you use some cryptic shorthand (a mere
number, for instance), you'll hate yourself in the morning, when you
have to constantly refer to a "decoder ring".
2) Silkscreen that name at every SMA connector to make connections
easy to understand and waveform names easy to record.
3) Don't forget to mark each board with a unique identifier as soon
as you get them (if you get multiple copies of the same board)
4) If possible, keep SMA connectors far enough apart that they
accommodate fat fingers - it makes connections MUCH easier for the
tightening & loosening processes.
5) The minimum spacing between SMAs must comprehend all mechanical
constraints - physical size of the connectors (including those of the
VNA cables, if attaching directly). This limits how close the
connectors of a "through" calibration structure can be, for instance.
6) Trace Features
a. There must be traces of different lengths on each layer
to be characterized, allowing Vp to be determined. The shortest and
longest possible traces should be used.
b. It is a good idea to have more than one instance of each
trace, since there can be substantial differences between traces.
c. For tightly-coupled (differential) traces, it doesn't
matter how long the traces are before coupling (within reason), as long
as that length is consistent, and 50ohms is maintained up to that point.
7) If you're characterizing a feature where the reference plane (in
this context, I mean the "ground" plane that your return current is on)
is changing (a via, for instance), make sure you surround that feature
with ground ("encapsulation") vias, so that you can include these in
your 3D models. Else, your nearest radiation boundary may be the ground
vias at your launch, and those may be much farther away than you want to
build into your model. =20
Note that these "encapsulation" vias should be farther away than you
expect to have return vias in your actual design. I.E., you don't want
to characterize a via with all these wonderful return path vias nearby
and have none on your actual design. Add return vias that are
representative of what you'll have in your actual design, separate from
the "encapsulation" vias.
8) For vias, double-check (and triple-check) whether pads on unused
layers are removed. You may or may not want them removed, but you want
to know for sure whether they were or not. As a default, I remove them
from the Gerbers before sending out to the board vendor, so I'm sure
they were removed.
9) For characterizing structures, plan on a short length of trace
(~100mils) being part of the "DUT" (and part of the 3D model). This
way, your 3D model "port" starts out in a TEM mode (or at least
quasi-TEM mode for microstrip), without edge capacitance effects. This
means that if you have a 3.1" trace leading into (and out of) your DUT,
your "open" standard would only be 3", and your "thru" standard 6". In
short, you never want your reference plane (in this context, I mean the
imaginary plane that delineates your "DUT" from your test system) at a
discontinuity.
10) Make sure you have a commitment from somebody to measure
everything they say is necessary on the board. You'll get lots of "It
would be good to...", until your board dimensions resemble a kitchen
table ("Feature Creep" is the technical term for this phenomenon - it
happens on products also). If you end up measuring and making sense of
half the wonderful stuff you've put on your board, you're doing well.
11) The lead-in up to the DUT must be as quiet as possible -
pico-probes, or well designed SMA-type connections. You can't de-embed
launches that are too noisy.
12) For the trace width and impedance, you'll probably be able to
specify one or the other exactly, but not both (the board vendor needs
some degree of freedom). Plan on some negotiation with the board vendor
to define geometries for each layer.
13) For characterizing stripline, layers near the bottom of the
board are preferred to reduce the via stub effects (if backdrilling
isn't available).
Good luck, and have fun!
Disclaimer:
The content of this message is my personal opinion only and although I
am an employee of Intel, the statements I make here in no way represent
Intel's position on the issue, nor am I authorized to speak on behalf of
Intel on this matter.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Jim Antonellis
Sent: Monday, January 02, 2006 1:13 PM
To: Si-List
Subject: [SI-LIST] Test PCB structures
Hello,
I am planning a PCB test structure board, primarily to validate my
tools, models and design rules for PCB xtalk, discontinuities (e.g. via
backdrilling) various SMA connector types, impedance controlled vias,
etc. etc.=20
Any suggetions, hints or bits of wisdom you may wish to send me is
appreciated as this is my first dedicated test fab and I would like to
minimize the "should-have, could-have, would-have" effect (notice I did
not say eliminate, but minimize %^)
Thx,
Jim
-
Jim Antonellis janton@xxxxxxxxxxxxx
Sandburst Corp www.sandburst.com
Office: 978.689.1669
Cell: 978.618.4745
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=20
=20
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