Using the probe right on the package may not get you the correct answer. I obviously don't know the details of your package. The traces you are trying to characterize may also have some of their return currents referenced to something other than the ground such as one of the power planes or there may be splits in the ground in your package. You really should in general be sure that the power and ground pins are all connected together. You should be able to remove the effects of any test fixture C by first recording the reference waveform with the package removed from the fixture and then measure the characteristics you need. The faster the TDR incident pulse the better. But if your method of connection to the DUT may not allow the full bandwidth of the TDR pulse to get to the circuitry of interest. One thing you need to remember is the model only needs to have enough bandwidth to cover the signals that will propagate through the package. If you have 100 psec rise and fall times you will need a model with 5GHz or so bandwidth. If your signals are 500 psec then 1 GHz or so should be adequate. Tom Dagostino Teraspeed Consulting Group LLC 503-430-1065 tom@xxxxxxxxxxxxx www.teraspeed.com -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Porsh Shih Sent: Monday, July 19, 2004 10:16 AM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] TDR on Package only Hi, 1. TDR a BGA package(PKG) with ball desoldered, and place probes on the = signal ball pad and a ground ball pad next to the signal's (no test PCB = involved) 2. TDR the same BGA package thru the test PCB with SMA, PCB trace, PCB ball = pad, and then the package itself (PKG is soldered on PCB) Assume the package substrate trace is 5mm and wire is 2.5mm long, TDR = pulse 35psec. Questions are: Can we really get the impedance profile of the package trace+wire by = using a 35psec Tr TDR? Or should we use sub 10psec TDR? The difference between 1 and 2 listed above as I can think of: a. Probe's ground, one is on PKG's and the other on PCB's b. The extra capacitance seen between PCB ball pad and the PCB ground (0.13pF per SpiceLink) Using ADS circuit simulator to TDR the cases above with and without = adding a capacitor of 0.13pF at entry point of the package trace, we see = when the cap is in place, the waveform gets a dip which masks out almost = the entire impedance profile of the package's at no-cap situation. Is it true that little cap between PCB and PKG interconnection dominates = the impedance profile of PKG's? Would like to get your opinions about package level impedance control = and verification. Thanks~ Porsh ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu