[SI-LIST] Strange non-monotonic edge after LVPECL and LVDS interface circuit
- From: luping liu <liewluping@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 20 Jun 2006 22:56:13 +0800 (CST)
Hi :
We need to interface the LVPECL to LVDS using
resistor network,the differential signal is a 155MHz
clock; the circuit looks like this :
______
3.3V-- |130ohm|-
------ |
| ______
---------------*--|56ohm |---*-----------
------ | _______
-|24.9ohm|--GND
-------
LVPECL_INPUT LVDS_OUT
______
3.3V-- |130ohm|--
------ |
| ______
---------------*--|56ohm |---*-----------
------ | _______
-|24.9ohm|--GND
-------
But a strange phenomena appears when we get the
driver and load's IBIS model from manufacturer and
simulate the interface circuit :
the differential signal after the resistor network
is non-monotonic(both rising and falling edge) ;
then at the load side (about 400mil trace)the
differential signal is monotonic.
Can anybody explain why it is happening ? Or
something wrong with our interface circuit ?
All the best ,
Liewluping
Best Regards，
Yours Robbie
^..^
(@@)
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