[SI-LIST] Re: Soldermask Impact Microstrip Impedance
- From: <Aubrey_Sparkman@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 6 Apr 2005 12:16:01 -0500
I just gotta throw in my 2 cents worth....
While others have made some good points, I wanted to add some comments
to help you decide whether including the solder mask in your
calculations is necessary.
Solder mask makes the least difference on very wide low impedance traces
spaced far apart. (anyone remember a memory bus with 28 ohm traces?)
Impedance difference here is very small, down in the measurement error
range.
Solder mask makes the most difference on very narrow high impedance
tightly coupled differential pairs; Impedance difference ~15% between
calculations with and without soldermask.
Aubrey Sparkman=20
Enterprise Engineering Signal Integrity Team
Dell, Inc.=20
Aubrey_Sparkman@xxxxxxxx=20
(512) 723-3592
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of ariazi
Sent: Wednesday, April 06, 2005 11:48 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Soldermask Impact Microstrip Impedance
Dear Peter Pang,
The soldermask coating on the top surface will increase the capacitance
=3D of the microstrip trace and hence decrease its characteristic
impedance.
It is stated in an article by Dr. Eric Bogatin, "When Accuracy Counts"
(Published in Printed Circuit Design & Manufacture May 2003, P. 36) that
Zo decreases by approximately 1 Ohm/0.001 inch of soldermask thickness.
The trace width, dielectric substrate thickness and its Er are regarded
=3D to possess first=3D20 order effect on Zo, whereas the effects of
soldermask and trace =3D thickness are of second order.
Best Regards,
Abe Riazi
ServerWorks
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
=3D On Behalf Of Pang Ning
Sent: Wednesday, April 06, 2005 6:21 AM
To: SI-LIST
Cc: Yang Wanguo(Tony); Tang Lan(Stella)
Subject: [SI-LIST] Soldermask Impact Microstrip Impedance
Dear experts,
I have a simple question for you about microstrip impedance. As you =3D
know, many impedance calculation tools didn't consider soldermask
influence =3D when counting microstrip impedance. Maybe the trace should
be called as =3D coated microstrip or embeded microstrip. Because the
dielectric constant of soldermask is much bigger than air, and
soldermask thickness is about 0.5mil~1mil, the real impedance on PCB
will be smaller than the =3D calculation results from simulation tools. =
So
would you please let me know how to =3D deal with this issue? Should the
soldermask influence be taken into =3D consideration when calculating
microstrip impedance? Thanks for your comments.
Thanks,
Best Regards,
Peter Pang
XGI Technology Inc.=3D20
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