[SI-LIST] Re: Simulating SI and PI through a "passive" backplane
- From: steve weir <weirsi@xxxxxxxxxx>
- To: bradb@xxxxxxxxxxx
- Date: Wed, 03 Mar 2010 02:02:05 -0800
Brad, a rail as I discussed is a single schematic net: Vss, Vddx,
etc. I do not mistake schematic nets for isopotentials.
Transverse voltage in the path be it from DC drop, or induction is not
an SI concern so long as:
1. Any noise EMF is common mode to both the signal and its return.
AND
2. The receiver reference:
a. Is the return, or
b. Floats on a constant offset from the return
AND
3. a. The receiver power source floats on the return OR
b. The receive signal and reference operate well within the CMR of the
receiver.
There are lots of ways to violate the above conditions. Exciting a
resonant structure with fast rise time signals is certainly one of the
more effective ones. In a bypass capacitorless backplane the lowest
frequency structures will by far be the power cavities. If in a single
net return path the daughter card to backplane connector return density
is so low that the return planes have a resonant frequency well below
0.3/Tr then in all likelihood cross-talk through the connectors has long
since killed the SI.
Best Regards,
Steve.
>
>
> You seem to be focusing on AC PI rather than DC IR drop.
>
> I believe you and I would say pretty much the same thing if we both typed
> more text, but I beg to differ with your brief text that says referencing to
> only one pwr or gnd net will preclude PDN issues.
>
> Whether you are defining a "rail" as a single net or a pair of nets I
> disagree. You can have resonances of the pair of nets, one or both of which
> you reference your signal to. These resonances couple noise in a more global
> sense into the signal from the PDN. Also, since there are other nets this
> global coupling implies you will have greatly enhanced signal-to-signal
> coupling near resonances. The PDN definitely enters into the picture for PDN
> resonances.
>
> Further, your signal may be referenced to a single net but if your have
> multi-layer transitions you may not have a clean return path local to the
> signal vias. Even if you have return current vias there can be a parasitic
> effects and if you pass through another plane you will launch noise into the
> PDN as parallel plate modes. If you don't have local return current vias for
> every signal via you will connect between planes through non-local vias or
> possibly decoupling capacitors. In any case, the PDN is entering into the
> picture.
>
> cheers,
> -Brad
>
>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
>> Sent: Tuesday, March 02, 2010 9:03 PM
>> To: Cuong P Nguyen
>> Cc: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Simulating SI and PI through a
>> "passive" backplane
>>
>> Cuong, as with many things: it depends. If any given signal
>> references only one rail through the entire channel path,
>> then the PDN never enters into the picture. If on the other
>> hand signals change or share references between multiple
>> power rails, then the PDN performance becomes a big issue,
>> biggest near the transitions.
>>
>> Steve
>> Cuong P Nguyen wrote:
>>
>>> Content-Type: text/plain;
>>> charset="us-ascii"
>>> Content-Transfer-Encoding: 7bit
>>> Anyone has any comments on simulating crosstalk on high speed diff
>>> pairs running through a "passive" backplane?
>>>
>>> The topology is as follow:
>>>
>>>
>>>
>>> 1. The driver resides on board #1.
>>>
>>> 2. This board connects to a passive backplane with
>>>
>> only connectors.
>>
>>> No other components (incl. decoupling)
>>>
>>> 3. The receiver is on board #2.
>>>
>>>
>>>
>>> My question is really on the effects of the GND and PWR
>>>
>> planes (on the
>>
>>> passive backplane) on the diff pairs and
>>>
>>> whether or not the crosstalk analysis will be accurately modeled.
>>>
>>>
>>>
>>> For Power Integrity Analysis, if the driver is on 1st board and
>>> receiver is on 2nd board and there are 2 connectors
>>>
>>> in between (with many pins inter-connecting the PWR and GND of the
>>> back plane to the PWR and GND of the
>>>
>>> 1st and 2nd board), how will the DC drop analyzed?
>>>
>>>
>>>
>>> Thanks for your feedback.
>>>
>>>
>>>
>>> ----------------------------
>>>
>>> Cuong Nguyen
>>>
>>> <http://www.edadirect.com/> edasmall2
>>>
>
>
>
--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
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