[SI-LIST] Re: Simulating SI and PI through a "passive" backplane
- From: Cristian Filip <cris_filip2002@xxxxxxxx>
- To: 'Cuong P Nguyen' <cuong@xxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx, Brad Brim <bradb@xxxxxxxxxxx>
- Date: Tue, 2 Mar 2010 20:04:19 -0800 (PST)
Hi Brad,
Can you please provide more details on how this works, not only for DC Drop
Analysis, but for AC Noise and impedance profile (with and without VRM) of the
system/board? I mean if you have a system where your power supply (DC/DC
converter) is sitting on a board, and the analysis is being done on another
board eventually connected through a backplane, what is the strategy for PI
analysis? When you have a single board, you calculate the target impedance
using the peak transient current, you add the VRM to your bear board (buried
capacitance) impedance and then you determine the number, value and type of
decoupling caps needed. That is straight forward, but in case of a multi-board
project there are questions that arise, regarding VRM modeling, parasitic
inductance and capacitance through the whole chain of power delivery network,
decoupling and bulk capacitors sitting on other board that the one being
analyzed, etc.
It will be appreciated if you provide more details about the right methodology
to follow for multi-board projects.
Thanks,
Cristian
--- On Tue, 3/2/10, Brad Brim <bradb@xxxxxxxxxxx> wrote:
> From: Brad Brim <bradb@xxxxxxxxxxx>
> Subject: [SI-LIST] Re: Simulating SI and PI through a "passive" backplane
> To: "'Cuong P Nguyen'" <cuong@xxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
> Received: Tuesday, March 2, 2010, 10:28 PM
> hello Cuong,
>
> a few DC IR drop tools support multi-board analysis, so
> what you want to do
> is well supported commercially
>
> cheers,
> -Brad Brim
> Sigrity
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
>
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Cuong P Nguyen
> > Sent: Tuesday, March 02, 2010 7:08 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Simulating SI and PI through a
> "passive" backplane
> >
> > Content-Type: text/plain;
> > charset="us-ascii"
> > Content-Transfer-Encoding: 7bit
> > Anyone has any comments on simulating crosstalk on
> high speed
> > diff pairs running through a "passive" backplane?
> >
> > The topology is as follow:
> >
> >
> >
> > 1. The driver resides
> on board #1.
> >
> > 2. This board connects
> to a passive backplane with only
> > connectors.
> > No other components (incl. decoupling)
> >
> > 3. The receiver is on
> board #2.
> >
> >
> >
> > My question is really on the effects of the GND and
> PWR
> > planes (on the passive backplane) on the diff pairs
> and
> >
> > whether or not the crosstalk analysis will be
> accurately modeled.
> >
> >
> >
> > For Power Integrity Analysis, if the driver is on 1st
> board
> > and receiver is on 2nd board and there are 2
> connectors
> >
> > in between (with many pins inter-connecting the PWR
> and GND
> > of the back plane to the PWR and GND of the
> >
> > 1st and 2nd board), how will the DC drop analyzed?
> >
> >
> >
> > Thanks for your feedback.
> >
> >
> >
> > ----------------------------
> >
> > Cuong Nguyen
> >
> > <http://www.edadirect.com/> edasmall2
>
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