[SI-LIST] SV: SV: Re: Copper Fill --- correction
- From: "Anders Ekholm (ERA)" <Anders.Ekholm@xxxxxxxxxxxxxxx>
- To: "'Jason D Leung'" <Jason.d.Leung@xxxxxxxxxxx>,"Anders Ekholm (ERA)" <Anders.Ekholm@xxxxxxxxxxxxxxx>
- Date: Fri, 14 Jun 2002 16:10:13 +0200
Well that would depend on your requirements on flatness of your PCBs, =
which
in turn would depend on your manufacturing lines for mounting =
components etc.
You probably have to talk to your manufacturing to get the requirement, =
and
talk to you board manufacturer on how much skew to expect from the =
actual design
you are working on. It depends a lot on the rest of your design how =
much it will skew.
Your physical stackup normally has to be symmetric. Physical asymmetric =
stack-ups
will normally skew/bend a lot.
If you are using microvias, uniform copper distribution will also =
increase you yield.
Since there is less risk of shortouts in the microvia layer, which is =
very thin,
if the cooper distribution is uniform.
And as Alex McPheeters correctly commented more copper and uniform =
copper will
improve your thermal characteristic. Your thermal goal on a PCB is to =
achive as
evenly spread thermal energy (heat) as possible, which is get as good =
thermal
conductivity as possible. More copper better thermal conductivity.
And of course you connect this balance copper to ground for EMI reasons =
if nothing
else. Which will in turn effect you traces impedance if a trace pass =
beneath or above
the balance copper. Thats one of the reasons to simulate your signal =
quality, balance
copper can ruin you signal quality if you do not watch out.
Simulating with ideal groundplanes will miss these effects.
Also watch out for balance copper the PCB manufacturer might add to get =
better
yield, which was not in your PCB database and therefore missed in your =
simulation.
This might get you some problems.
Regards /Anders Ekholm
-----Ursprungligt meddelande-----
Fr=E5n: Jason D Leung [mailto:Jason.d.Leung@xxxxxxxxxxx]
Skickat: den 14 juni 2002 15:43
Till: Anders Ekholm (ERA)
Kopia: scott@xxxxxxxxxxxxx; RayCaliendo@xxxxxxxxxx; silist
=C4mne: Re: SV: [SI-LIST] Re: Copper Fill --- correction
Hi Anders Ekholm:
thanks
then how do we know when it is necessary for us to have copper balance, =
and how much
copper we should be using to do the job
best Regards
Jason
"Anders Ekholm (ERA)" wrote:
> Hi.
> For other reasons than Signal Integrity ones, we want a uniform =
copper distribution
> on the PCB, since otherwise it will bend. A uniform copper =
distribution is good
> for mechanical reasons.
>
> Regards /Anders Ekholm
>
> -----Ursprungligt meddelande-----
> Fr=E5n: Jason D Leung [mailto:Jason.d.Leung@xxxxxxxxxxx]
> Skickat: den 14 juni 2002 15:00
> Till: scott@xxxxxxxxxxxxx; RayCaliendo@xxxxxxxxxx
> Kopia: silist
> =C4mne: [SI-LIST] Re: Copper Fill --- correction
>
> Hi guys,
> I understand that if the fill is too close to the signal trace it is =
going
> to increase the capacitance and decrease the impedance in turn.
> But my question will be why do we need to put a fill on the pcb. ( =
this may
> be a basic question , and I always heard my colleagues saying it, but =
it
> helps me alot, if there's a kind soul to help me to understand it)
>
> thanks in advance
> Regards
> Jason
>
> Scott McMorrow wrote:
>
> > Okay, now I really need some coffee ... and it's 5:30 in the =
evening.
> > Here's yet another correction and more elaboration.
> >
> > A square patch of copper on top of a dielectric and plane forms a =
crude
> > cavity resonator which will have a number of natural resonant
> > eigenmodes. The first resonant point is a half-wave resonance. =
The
> > resonance frequency is equal to the round trip of a wave =
propagating
> > back and forth across the region, much like what would happen in a
> > square pool of water between the two walls. For a one square inch =
patch
> > of copper, the resonant frequency on FR-4 is somewhere between 2.7 =
and
> > 3.3 GHz
> >
> > A very crude square patch
> >
> > w
> > --------------
> > | | resonant frequency =3D 1/( 2 * w * Vp)
> > | | Vp =3D velocity of propagation of wave =
in
> > dielectric medium =3D c/sqrt(Er)
> > | | w =3D width and height of square
> > | |
> > | |
> > ---------------
> >
> > Adding vias to the patch effectively pins the structure down and =
raises
> > it's resonant frequency. The spacing of the vias control the =
resonance,
> > with a half-wave resonance being the lowest generally supported by =
the
> > structure. Stitching the patch at all four corners actually does =
nothing
> > to change the resonant frequency of the cavity. However, placing a
> > fifth via at the center will push the resonance up by a factor of =
2.
> >
> > w
> > @------------@
> > | | resonant frequency =3D 1/( 4 * w * =
Vp)
> > | | Vp =3D velocity of propagation of =
wave in
> > dielectric medium
> > | @ | w =3D width and height of square
> > | | @ =3D Via stitch
> > | |
> > @------------@
> >
> > In essence, the via spacing has changed from w to w/2. These =
formulas
> > are quite approximate, but will place us in the general playing =
field. A
> > full-wave field solver such as PowerSI from Sigrity, or SIwave and =
HFSS
> > from Ansoft, will provide much more exact resonance frequency =
analysis.
> >
> > So, the "rough" formula I gave for via spacing should be:
> >
> > via spacing =3D1/(2 * (f * Vp)) not 2/(f * Vp) as I had indicated.
> >
> > In my previous example, this would amount to a via spacing of 0.59
> > inches, not 1.18.
> >
> > Sorry about my confusion.
> >
> > Scott
> >
> > --
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 2926 SE Yamhill St.
> > Portland, OR 97214
> > (503) 239-5536
> > http://www.teraspeed.com
> >
> > Scott McMorrow wrote:
> >
> > > My equation below has an error.
> > >
> > > The maximum via spacing should be:
> > >
> > > 2/(f * Vp)
> > >
> > > This accounts for the half-wave resonance which occurs between =
vias.
> > >
> > >
> > > regards,
> > >
> > > Scott
> > >
> > >
> > > Scott McMorrow wrote:
> > >
> > >> Ray,
> > >>
> > >> When the separation of the copper fill from any signal is > 20 =
times
> > >> the signal-to-plane spacing there is no effect on the signals. =
So,
> > >> for 5 mil dielectric thickness, the fill area to signal trace
> > >> clearance should be 100 mils or greater. I would also suggest
> > >> grounding each fill area at multiple points to eliminate =
possible EMI
> > >> coupling problems.. At a minimum, use ground stitch vias at =
four
> > >> corners to contain resonances of the fill area. For extremely =
high
> > >> speed multi-gigahertz systems, the vias should be spaced a =
maximum
> > >> distance apart of 1/(f * Vp) apart. Where f =3D the upper =
frequency of
> > >> operation and Vp is the velocity of propagation of signals =
within the
> > >> dielectric.
> > >>
> > >> For FR4 Vp is around 180ps/in. For 3.125 Gbps signallling the =
upper
> > >> frequency you are concerned with is the 3rd harmonic of the =
switching
> > >> frequency, 4.68 GHz. In this case, the maximum stitch via =
spacing
> > >> would be
> > >> 1/(4.68e9 * 180e-12) =3D 1.18 inches.
> > >>
> > >> Best regards,
> > >>
> > >> Scott
> > >>
> > >>
> > >>
> > >>
> > >
> >
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