[SI-LIST] Re: SSO SSTL Vs LVTTL
- From: "Larry Smith" <LSMITH@xxxxxxxxxx>
- To: <james.f.peterson@xxxxxxxxxxxxx>, "Canes Venatici" <starsilic@xxxxxxxxx>
- Date: Fri, 4 May 2007 11:21:31 -0700
Canes - thanks for your off-line invitation to comment on this thread.
After looking through it, I feel that Jim Peterson has given some very
sound answers. Let me see if I can expand on them a little.
SSN simulation is complicated and your results completely depend upon
how you set up the simulation and where you measure results. It is
important to evaluate the rise (fall) time of the aggressor drivers and
make sure that they are loaded in an appropriate manor for a time period
that is at least double the rise time, as Jim has suggested. In all
likelihood, the load will be a 50 Ohm transmission line for this time
period. The SSN that gets launched into the near-end of the
transmission line does not depend upon the loading at the far-end
because the driver does not feel the effects of the far-end until 2
time-of-flights have passed. =20
For example, consider a driver with 500pSec rise time connected to a 3
inch transmission line. The driver does not feel the effect of the
far-end load until 2 time-of-flights (1 nSec) has passed. By that time,
the driver has done whatever it is going to do and has parked at a
temporary voltage, awaiting the results of the reflection from the far
end. If you want to find the SSN noise that is launched into a 50 Ohm
transmission line, just use a 50 Ohm resistor for the load for both
aggressors and victim. But 50 Ohms to connected to what? It depends
upon the load topology. LVTTL, SSTL class 1 and SSTL class 2 are very
different because the initial conditions for each are different (DC
voltages and pre-charge currents). So the 50 Ohm resistance that mimics
the transmission line has to be carefully attached to the appropriate
voltage.
The best bet is to simulate the exact circuit topology that you are
interested in. You are probably interested in the SSN waveforms for the
load at the far end of the transmission line so you probably don't want
to substitute anything else for the transmission line. You probably
want to use lossy transmission lines (i.e. W-element) because the high
frequency SSN spikes associated with sub-nSec rise times will definitely
be attenuated as they go down the transmission line. This is
particularly true for LVTTL where multiple reflections will be seen from
a simulation of an ideal t-line element but die out pretty quickly with
lossy w-element model for transmission line. =20
Also, bear in mind that SSTL class 2 drivers are likely to be 25 Ohms
compared to 50 Ohms for SSTL class 1. The stronger drive strength
produces more SSN. =20
It's a jungle out there.. It is very difficult to state any
generalities about SSN until your specifics of load topology, drive
strength and rise times are known. You're results will depend greatly
on these parameters.
Regards,
Larry Smith
Altera Corporation=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Peterson, James F (EHCOE)
Sent: Thursday, May 03, 2007 4:55 AM
To: Canes Venatici
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SSO SSTL Vs LVTTL
Good question...(what should the test load be for a SSO simulation, or
measurement?)
=20
I think the type of load should be as close to the load of the actual
circuit as possible. So a 50 ohm transmission line, that's 2x longer
than the rise time should be a decent place to start.... I choose 2x the
length of the rise time so that the driver will completely "feel" the 50
ohm load (if rise time is 500ps, then a 6 inch t-line would be good).
=20
You also need some way to measure current. Some SI simulators have a
current mode selection (as opposed to the normal voltage mode) that the
user can select. The simulation then shows the current spike in the
circuit as the buffer toggles... To measure it...hmm, I don't think a
current probe is quick enough to see these small current spikes - you
might need a ~1 ohm series resistor that you can measure the voltage
drop on with a couple hi-f scope probes.
=20
Anyone have any other suggestions?
=20
Regards,
Jim Peterson
Honeywell
=20
________________________________
From: Canes Venatici [mailto:starsilic@xxxxxxxxx]=20
Sent: Thursday, May 03, 2007 5:49 AM
To: Peterson, James F (EHCOE)
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] SSO SSTL Vs LVTTL
=20
Jim,
Thanks for your answer. I want to explain in-depth, why I considered
cap. of T.line.
FYI, I'd not lumped the transmission line i/p capacitance as a load cap.
First, I'd put transmission line
at the o/p of the driver and seen the rise time at the i/p of
T.line(Tr), just before the reflection causing the
near end signal getting distorted.=20
Then I'd swept the lumped load cap (replaced T.Line load) at the o/p of
driver and seen where the rise=20
time matches. I could find some value. It matched exactly with the
calculated capacitance of T.Line=20
(C=3DTd/Zo). Then I assumed L can also be calculated similarly, =
(L=3DTd*Zo).
------------------------ Calculations---------------
I assumed 4in lossless transmission line, Prop. velocity =3D 1.5e8 m/s,
Zo=3D50.
So 666.6ps is the delay and C=3D 13pF, L=3D33.3nH
--------------------------------------------------------
Our first problem was whether we need lumped model or distributed model
for the load. For that I calculated the
electrical length (length of rising edge), by Tr/[delay(ps/in)]. I'd
seen the rise time and length of transmission
lines makes me to use distributed model (trace length >=3D electrical
length/2).=20
This made me to ask the question below,
I could see in some documents, the SSO simulation set up for SSTL2
interface is like below.
I want to know whether the schematic below represents the correct
simulation set-up for SSTL2 quite node
SSO simulation including T.line effects.=20
I tried inserting transmission line between Rser and Cload-Rt junction.
But I get very different values
of noise compared to the results provided in the doc, which is using the
below set-up.
Could anyone explain which is correct method and how the schematic below
can represent the
T.Line effects.=20
Actually in the simulation I'd added the package modeling for power
distribution also, but not shown here.
=20
VTT
=20
____
=20
|
=20
|
=20
/
=20
\ Rt
=20
/
=20
\
------------ ----------
|
| | | | Rser
|
| Driver |-------| Pkg | ------------/\/\/\/\/\/\----------|
| | | model |
|
| | | |
|
------------ ------------
|
=20
=3D=3D=3D=3D Cload
=20
| =20
=20
|=20
=20
|=20
=20
_____
=20
__
=20
-
Regards
Canes
----- Original Message ----
From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: Canes Venatici <starsilic@xxxxxxxxx>
Sent: Wednesday, May 2, 2007 5:34:19 PM
Subject: RE: [SI-LIST] SSO SSTL Vs LVTTL
Canes,
=20
That's the beautiful and remarkable thing about transmission lines. They
do not distort, only delay. The reason they don't distort is because
the t-line looks resistive, not capacitive or inductive. And, indeed,
this is what the edge of your signal sees (not the steady state portion
of your signal).
=20
For a couple references see page 143, last paragraph, of Dr. Johnson's
book "High Speed Digital Design -Black Magic" and the last 2 paragraphs
of page 295 of Ron Poon's "Computer Circuits Electrical Design".
=20
If you have a 10 inch t-line at 4pf per inch, you can't add up the C per
inch and replace it with a 40pf cap because "the capacitive effect is
tuned out by the inductive effect, and the ladder network just acts as
an ideal delay line : it does not degrade the signal risetime and
falltime" (R. Poon).
=20
Jim Peterson
=20
________________________________
From: Canes Venatici [mailto:starsilic@xxxxxxxxx]=20
Sent: Wednesday, May 02, 2007 3:03 AM
To: Peterson, James F (EHCOE)
Subject: Re: [SI-LIST] SSO SSTL Vs LVTTL
=20
Jim,
Could you tell me why, for the drivers the T-lines are seen as resistive
load?
Why I'm asking is during transients only SSN occurs. During that time,
the
drivers see the T.Lines as inductors and capacitors/unit length, is my
understanding.
Probably during steady state they (T.Lines) can be seen as resistive
loads.
Could you correct/explain me if I'm wrong?
Regards
Canes.
----- Original Message ----
From: " Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: starsilic@xxxxxxxxx
Sent: Tuesday, May 1, 2007 1:05:55 AM
Subject: RE: [SI-LIST] SSO SSTL Vs LVTTL
From what I have seen, and it's mostly been the results from simulators
and what I've read, so I don't have a lot of lab data to back this up,
using this approach of approximating the SSO current with the source
impedance is pretty accurate...that said, you do have to figure out what
the source-Z is, but there are a couple excellent ways to do that.
=20
Your second paragraph below is not clear to me. I'm not sure I
understand the question, but remember that to a driver, t-lines look
resistive, not capacitive or inductive. You can't lump together the C
and L.
=20
-Jim
=20
________________________________
From: Canes Venatici [mailto:starsilic@xxxxxxxxx]=20
Sent: Monday, April 30, 2007 9:13 AM
To: Peterson, James F (EHCOE)
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] SSO SSTL Vs LVTTL
=20
Jim Peterson,
Thanks for your reply. The only concern is the impedance of the driver
may be non-linear,
depending upon the state (cut-off/linear/saturation) of the transistors,
so I was wondering
can we approximate the driver impedance.
Also I've one more doubt regarding the simulations using T.Lines. I used
4inch lossless transmission line.
The equivalent i/p inductance comes around 33nH and capacitance comes to
be 13pF, by simple formulas
of T.lines. With this if I do simulations, I get very high power cell
requirement for each signal cell, or the quite node
noise is very high.
I could see in some docs related to SSO simulations, they were just
putting series resistor at the output of the driver, followed by
termination resistor pulled to Vtt for SSTL interfaces, instead of
T.lines in their SSO set-ups.=20
Could anyone clarify on how well it can represent SSO noise simulations?
Regards
Canes
----- Original Message ----
From: " Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Cc: starsilic@xxxxxxxxx
Sent: Monday, April 30, 2007 5:07:14 PM
Subject: RE: [SI-LIST] SSO SSTL Vs LVTTL
Hello Canes -
Since you're measuring noise at a quiet node, I assume you are
discussing SSO noise. I'm going to step out a little here and make a
bold statement : if you are comparing the SSO characteristics of two
different technologies, say 2.5V LVTTL and 2.5V SSTL, and their rise
times are the same, and their source impedances are the same, then their
SSO noise will also be the same. So, based on that statement, changes in
these above mentioned items will cause the SSO to change. If you go to a
stronger driver or a larger voltage swing (3.3V LVTTL) - and the rise
time stays the same - then you've increased SSO noise. If you go with a
weaker driver, or you put a series resistor at the output (like SSTL)
then the SSO noise will decrease. Signal swing, rise/fall time, and
source-Z are the things that influence SSO noise.
As a side note, you mention "12ma driver". IC manufacturers use this as
a DC drive number not an AC number. That's why we should use the source
impedance of the driver as a better (but not perfect) description of a
driver's capability.=20
Regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Canes Venatici
Sent: Monday, April 30, 2007 1:18 AM
To: si-list@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SSO SSTL Vs LVTTL
Hi,
I did quite node simulations in LVTTL and SSTL class I and II pads. I
used transmission line models for all the=20
simulations with noise measured at the Far End.
I tried to operate the LVTTL pads at 3.3V with 12mA drive strength. I
could see
the noise is more than with SSTL2-I/II interface.=20
Since there were no terminations for LVTTL, I suspect it can give more
noise compared to=20
SSTL. Comments are appreciated.
Even between SSTL2-I and II the power:signal is nearly same (the quite
node noise is similar),=20
with class-II is slightly more than class-I and in lower power:signal
ratios, the noise is less in=20
class-II compared to class-I.=20
I feel SSTL2-class-II have two terminations, which makes the interface
less noisier compared
to SSTL2-Class-I. Comments are appreciated.
Regards
Canes
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