[SI-LIST] SI engineer job opportunities at Hisilicon (huawei) in Shanghai or Shenzheng, China

  • From: yinhongcheng <yinhc@xxxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 06 May 2008 15:22:30 +0800

Hi All,
 
Please contact Me directly if you are interested.  

Here is a general job responsibility Description: 



1.        Evaluation and choice of 3rd party IO buffer and SerDes IP for ASIC 
design.

2.        Definition of board level network topologies. 

3.      Creation of interconnect models. 

4.        Creation of Hspice circuit simulation decks. 

5.      Simulation of these Hspice decks and output IO buffer delay, transition 
timing parameters.

6.        Lab debug of signal integrity, noise and/or timing issues. 

7.      Definition of the ASIC IO pad ring. 

8.        Understanding the ASIC power sequencing requirements. 

9.     SI guidelines for package design. 

10.  Documentation. 

 

Requirements: 



1.        BSEE or BS Physics is required, an MS or PhD is preferred. 

2.        2 years of hands-on circuit level simulation experience with Hspice. 

3.        2 years of experience in signal integrity analysis. 

4.      understanding of both the theoretical and real-world aspects of 
electromagnetic field theory, transmission lines, crosstalk, ISI, SSN, jitter 
and other signal integrity phenomena is a plus.

5.      Experience with serial communication standards and protocols is 
required; experience with SerDes implementations and experience with the PCI 
Express and XAUI interfaces is a plus.

6.        Experience with high-speed digital communication standards is 
required; experience with CML, LVDS, SSTL, HSTL and PCI specifications is a 
plus. 

7.      Experience with semiconductor IO circuit design is a plus. 

8.        Experience with package design and analysis is is a plus. 

9.        Experience with 2D and 3D field solvers is a plus. 

10.  Practical, hands-on experience with high-speed lab test equipment is a 
plus.

11.  Experience in taping out multi-million gate CMOS ASICs in 130nm technology 
and below, an understanding of the IC signal integrity effects present in these 
technology nodes and familiarity with the design flows is a plus.








------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: