[SI-LIST] Re: Referencing multiple voltages in a stackup
- From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 22 Oct 2004 10:17:02 -0700
The 1.5V plane is a core voltage but it is for an embedded processor.=20
In your example, would both 3.3V and 1.5V signals be safe to route on
Sig1?
What I am getting confused by is what some of you mean by "critical
signals". Let's assume that they are all critical to the function of
the board, so I think of them all as critical. If you mean "critical"
based upon their speed, let's say some are running at 133MHz (1 ns rise
time) and some are running at 266MHz (500ps rise time).
Thanks,
Chris
> -----Original Message-----
> From: Ken Cantrell [mailto:Ken.Cantrell@xxxxxxxxxxxxxxxx]=20
> Sent: Thursday, October 21, 2004 6:50 PM
> To: weirsp@xxxxxxxxxx; Chris McGrath; si-list@xxxxxxxxxxxxx
> Subject: RE: [SI-LIST] Re: Referencing multiple voltages in a stackup
>=20
>=20
> Chris,
> If the 1.5V plane is the core voltage for a big mega-gate=20
> FPGA, I would be more concerned about the 1.5V noise leaking=20
> into the I/O since the core current is significantly larger=20
> than the I/O current. I never stack them together. I use=20
> something like
>=20
> Top (sig)
> Gnd
> 1.5V
> Sig1
> 3.3V
> Sig2
> Gnd
> and on down the stack.
>=20
> Ken
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
> Sent: Thursday, October 21, 2004 4:01 PM
> To: chris.mcgrath@xxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Referencing multiple voltages in a stackup
>=20
>=20
> Chris,
>=20
> You need to be very careful with that proposal. In a perfect=20
> world, signals return only against the reference ( typically=20
> ground ) for the I/O, and only operate on one side of that=20
> reference plane. It is not much worse to operate on both=20
> sides of the plane. The antipad for the signal via typically=20
> provides the return signal path from one side of the plane to=20
> the other.
>=20
> Substantively worse is the common practice of offset=20
> striplines in a Vcc Sig Sig Gnd sandwich. Most of the return=20
> current has to work its way to nearby decoupling capacitors=20
> on the surface and back down to the opposing power layer. =20
> This works OK for non-demanding signals, but makes for=20
> resonant cavities that can be vexing.
>=20
> Then we get to what I understand as your proposal. Be=20
> afraid, be very afraid. For that proposal to fly, you need=20
> to thoroughly evaluate the effective inductance between=20
> whatever chunk of metal you are attempting to use as an image=20
> plane and the rest of the return signal path, and be able to=20
> show that the L*di/dt is not going to first create an EMC=20
> nightmare and secondly will not create signaling problems. =20
> You could readily create a situation where no amount of=20
> decoupling will make the board work.
>=20
> Steve
> At 02:09 PM 10/21/2004 -0700, Chris McGrath wrote:
>=20
> >I'm putting together a stackup with roughly 20 layers that requires=20
> >distribution of five different voltages and I'm wondering=20
> what effect=20
> >running 3.3V logic (133MHz) adjacent to a lower voltage=20
> reference plane=20
> >(such as 1.5V) would have on the lower voltage reference plane. =3D20
> >
> >I understand the concept of the power plane operating as a reference=20
> >plane, but with 4 mil cores throughout the board, I am worried about=20
> >coupling switching noise from 3.3V signals into lower=20
> voltage reference=20
> >planes adjacent to the 3.3V signals. =3D20
> >
> >As I see it, the conservative approach would be to only route 3.3V=20
> >signals next to the 3.3V plane or next to a ground plane. However,=20
> >given the rise times involved (~ 1ns), I tend to believe that=20
> >sufficient decoupling and stitching together of ground planes in the=20
> >area would suppress any noise that could potentially couple into the=20
> >lower voltage planes. My understanding is that for the higher speed=20
> >signals (over 1 GHz), it is not wise to route adjacent to=20
> any reference=20
> >other than ground and the voltage reference for the GHZ signals. My=20
> >question mainly revolves around signals running at less than 1 GHz.
> >
> >I am interested in hearing any opinions you may have on the=20
> topic. We=20
> >often talk about stackups but I could not find anything in=20
> the archives=20
> >that addressed the issue of stackups with a number of different=20
> >voltages.
> >
> >Thanks,
> >Chris
> >
> >
> >------------------------------------------
> >Chris McGrath
> >Sr. Hardware Engineer
> >ADIC
> >ph: (607) 241-4858
> >eM: chris.mcgrath@xxxxxxxx
> >------------------------------------------
> >------------------------------------------------------------------
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