[SI-LIST] Re: RF ground in RF chip

  • From: Bi Han <mike_bihan@xxxxxxxxxxxx>
  • To: "Swanson, Dan" <Dan.Swanson@xxxxxxxxxx>,List` Si <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 3 Sep 2003 08:18:25 +0800 (CST)

Dear Dan:
The CPS mentioned in the mail was used in silicon CMOS chip. The ground trace 
was used to lower the loss of signal trace, by attacting the eletrical lines 
from penetrating lossy substrate. CPW was better choice but occupies too much 
space and CPS is the trade off choice.
 
As I mentioned in last mail, the ground trace was non ideal ground reference 
actually, which will do harm to the performance. Can I tap the substrate, which 
is a very hugh capacitor, to the ground trace, to make it better ground?
 
Han
"Swanson, Dan" <Dan.Swanson@xxxxxxxxxx> wrote:
Dear Bi Han

Your problems with CPS are similar to those
with CPW. "Pure" CPS would have no ground plane
near by. Adding a local ground plane allows 
additional, unwanted modes. Tieing the CPS ground
strip to a microstrip groundplane will result
in a structure that really is not CPS anymore.

If you want pure CPS, a transition to go from
microstrip to CPS can be found in:

"Coplanar Stripline Resonators Modeling
and Applications to Filters" Suh and Chang
MTT Transactions, May 2002, pp 1289-1296.

Dan

Dan Swanson EMAIL: d.swanson@xxxxxxxx
Andrew Corp. PHONE: 978-834-4085
37 South Hunt Road FAX: 978-388-7077
Amesbury, MA 01913


> -----Original Message-----
> From: Bi Han [mailto:mike_bihan@xxxxxxxxxxxx]
> Sent: Monday, September 01, 2003 12:58 AM
> To: List` Si
> Subject: [SI-LIST] RF ground in RF chip
> 
> 
> What¡¯s the question?
> 
> In high speed or RF integrated circuit design, sometimes we 
> need to use very long transmission lines in the chip, such as 
> distributed amplifier. What we need to in the very first step 
> is to model the transmission line.
> 
> For example, we are planning to use CPS(coplanar stripe line) 
> as the compensation element in the circuit. 
> 
> 
> 
> Issue?
> 
> The difficulty was that the ground metal trace in the CPS 
> line will be difficult to deal with. We have made experiment 
> to extract the RLGC model of the CPS in two ways. 
> 
> 
> 
> First, we just made the ground trace as ideal ground. 
> 
> Second, we model the ground trace as lossy signal line whose 
> two terminals was grounded. 
> 
> 
> 
> The simulation results showed that the loss of the metal 
> ground will make the crosstalk and loss of transmissions 
> greater. This lead to a interesting way to improve the 
> performance of CPS in the chip. 
> 
> We just want to give a better grounding to the CPS¡¯s ground 
> trace, we use stacked vias at the outside of ground trace to 
> connect top metal to the substrate.
> 
> 
> 
> Do you think that helpful? 
> 
> 
> 
> The answer may lead to the questioning where is the 
> acceptable ground in RF chip?
> 
> 
> 
> Thanks!
> 
> Yours sincerely,
> 
> 
> 
> 
> 
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