[SI-LIST] Re: Quick switch
- From: bmgman <bmgman@xxxxxxxxxx>
- To: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
- Date: Fri, 30 May 2008 18:37:53 -0500
Peterson, James F (EHCOE) wrote:
>This is a little off the SI topic related to these FET switches, but I
>would also want to understand how I select one of these clocks, by
>enabling one these switches, without initially causing a sliver of a
>clock pulse to propagate out to my flops.
>
>
Verrrry Carefully!
The switch control must be synchronous to both clocks. The enabled
clock is disabled synchronous to its inactive edge; the presently
disabled clock is enabled synchronous to its inactive edge after the
newly-selected clock has synchronized the fact that the other clock is
disabled. There's a period of perhaps one-two cycles where no active
clock edges occur.
It helps if the termination on the multiplexed clock line is to the
inactive state of the clock, otherwise the termination introduces
transitions onto the clock line. Series-terminated clock lines are not
much of an issue if the clock period is short enough. The line and load
C hold the inactive level while the control logic is changing the clock
source. Leakage can cause the level to drift if the switches are left
disabled for too long.
It works reliably if care is taken in the design. If not, all bets are off.
Mike
- - - - - -
>Jim Peterson
>Honeywell
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Scott McMorrow
>Sent: Friday, May 30, 2008 9:19 AM
>To: steve weir
>Cc: ravi.potana@xxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Quick switch
>
>Ravi
>To follow on with what Steve has said, most FET switch packages do not=20
>have adequate package grounding. Since the substrate is normally=20
>grounded, this poses a problem, since there is parasitic capacitive=20
>coupling between each switch and the substrate. These are fairly easy=20
>devices to model in SPICE, and many manufacturers provide accurate=20
>models. IBIS models, however, cannot adequately model these devices.
>
>regards,
>
>Scott
>
>Scott McMorrow
>Teraspeed Consulting Group LLC
>121 North River Drive
>Narragansett, RI 02882
>(401) 284-1827 Business
>(401) 284-1840 Fax
>
>http://www.teraspeed.com
>
>Teraspeed(r) is the registered service mark of
>Teraspeed Consulting Group LLC
>
>
>
>steve weir wrote:
>
>
>>An NFET or CMOS switch in a package has parasitics like any other=20
>>device. If you model and work within the limitations of those=20
>>parasitics you shouldn't have any unwelcome surprises. If you pretend
>>
>>
>
>
>
>>that the device is without parasitics you can easily make designs that
>>
>>
>
>
>
>>run into problems.
>>
>>Steve
>>ravi.potana@xxxxxxxxx wrote:
>> =20
>>
>>
>>>Hello All,
>>>=20
>>>Please let me know if anyone has used Quick switch (FET based) on
>>>
>>>
>clock
>
>
>>>with frequency 125MHz for muxing operations and seeing any SI issues
>>>
>>>
>on
>
>
>>>the clock line after passing through the FET Switch.=20
>>>=20
>>>regards
>>>Ravi
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