[SI-LIST] Re: Parallel Inductor in Capacitor !!!
- From: Thomas Savarino <thomas.savarino@xxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 13 May 2011 09:55:13 -0700
I'm really curious how this lumped model was synthesized.
so, how was it synthesized?
best
ts
On May 13, 2011, at 9:48 AM, Ray Anderson wrote:
> Schematic of the model can be seen here:
> https://sites.google.com/site/wb6tpu2/home/decap_schematic-1
>
> (click on the Attachment "View" link)
>
> -Ray
> Xilinx Inc.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Jory McKinley
> Sent: Thursday, May 12, 2011 8:03 PM
> To: Andrew Ingraham; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Parallel Inductor in Capacitor !!!
>
> Hello Andy,
> It looks like a model fit with these pairs in parallel:
> L6 and C6 in parallel
> L7 and C7 in parallel
> L8 and C8 in parallel
> -Jory
>
>
>
>
> ________________________________
> From: Andrew Ingraham <a.ingraham@xxxxxxxx>
> To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
> Sent: Thu, May 12, 2011 7:40:50 PM
> Subject: [SI-LIST] Re: Parallel Inductor in Capacitor !!!
>
> Did you trace out the subcircuit? Those inductors (in fact all four
> of them) are in series with C1.
>
> Andy
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