[SI-LIST] Re: Parallel Inductor in Capacitor !!!
- From: Ray Anderson <ray.anderson@xxxxxxxxxx>
- To: Thomas Savarino <thomas.savarino@xxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 May 2011 10:22:15 -0700
Thomas-
I'm not sure exactly what tool Murata used to generate their model (I
suspect it may be an internal proprietary tool), but a number of
commonly available tools like Agilent ADS, Ansys Designer, Sigrity BBS
and others have the ability to read in a set of s-parameter data and
then synthesize a spice compatible model with various topologies
utilizing some sort of vector fitting or optimization algorithm.
You could also schematically define your own assumed topology and then
using either the Tune or Optimization capabilities of a tool like ADS
generate your own model by tweaking the element values of your assumed
topology circuit to match the simulated s-parameters of that model to
the measured s-parameters you want to model.
-Ray
Raymond Anderson
Senior Signal Integrity Staff Engineer
Programmable Platforms Development
Silicon Technology Group
Signal Integrity and Package Development Department
Xilinx Inc.
2100 Logic Drive
San Jose, California 95124
(408) 626-6277
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Thomas Savarino
Sent: Friday, May 13, 2011 9:55 AM
To: si-list@xxxxxxxxxxxxx
Cc: Thomas Savarino
Subject: [SI-LIST] Re: Parallel Inductor in Capacitor !!!
I'm really curious how this lumped model was synthesized.
so, how was it synthesized?
best
ts
On May 13, 2011, at 9:48 AM, Ray Anderson wrote:
> Schematic of the model can be seen here:
> https://sites.google.com/site/wb6tpu2/home/decap_schematic-1
>
> (click on the Attachment "View" link)
>
> -Ray
> Xilinx Inc.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Jory McKinley
> Sent: Thursday, May 12, 2011 8:03 PM
> To: Andrew Ingraham; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Parallel Inductor in Capacitor !!!
>
> Hello Andy,
> It looks like a model fit with these pairs in parallel:
> L6 and C6 in parallel
> L7 and C7 in parallel
> L8 and C8 in parallel
> -Jory
>
>
>
>
> ________________________________
> From: Andrew Ingraham <a.ingraham@xxxxxxxx>
> To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
> Sent: Thu, May 12, 2011 7:40:50 PM
> Subject: [SI-LIST] Re: Parallel Inductor in Capacitor !!!
>
> Did you trace out the subcircuit? Those inductors (in fact all four
> of them) are in series with C1.
>
> Andy
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