[SI-LIST] Re: PCI Express reference clock, is it needed?
- From: Pehr Andersson <andersson.pehr@xxxxxxxxx>
- To: "T.K. Jeon" <tkjeon@xxxxxxxxxxx>
- Date: Wed, 21 Dec 2011 17:48:54 +0100
Thank you all for your answers!
So to recap.
1) If we want we could use no reference clock at all, but this depends on
the how good is the SERDES.
2) For SSC, a reference clock is necessary
3) According to PCIe CEM specification, we need a 100MHz differential clock
routed to the PCI connector.
Best regards, Pelle
2011/12/14 T.K. Jeon <tkjeon@xxxxxxxxxxx>
> Hello Pelle,
>
> When the link is in the active state, the PLL is locked to incoming data.
> However, when Rx sees either idle signal or signal loss, the link gets into
> the standby mode and the PLL is locked to the reference clock. PCI Express
> has limited latency to exit the standby mode and the clock needs to be
> ready before the exit occurred.
>
> In addition, the reference clock is used to clock the internal gates.
> Thus, Rx has two clock domains(i.e. the ref clk domain and the recovered
> clk domain). That's where the elastic buffer comes into play for smooth
> transitioning between the two domains in the PCI express.
>
> Regards,
> TK
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Pehr Andersson
> Sent: Tuesday, December 13, 2011 4:16 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] PCI Express reference clock, is it needed?
>
> Hello dear readers, I have maybe a silly question that has been
> bugging me for a while, hopefully it will get answered so it's not
> bugging me anymore :).
>
> For PCI Express it is stated that the clock signal is embedded within
> the data signal.
>
> Why do we then need to route reference clock (REFCLK), that is an
> external clock signal for PCI Express?
>
> Would PCI Express data communication work even if we didn't have
> REFCLK? Say it we go over a cable for instance.
>
> Thank you for you time,
> Best regards, Pelle
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