[SI-LIST] Origin of Return Loss In SERDES Spec's

  • From: edward kowal <kowal_edward2007@xxxxxxxxxxx>
  • To: SI LIST <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 15 May 2015 11:32:44 -0700

Experts,

I have a few questions about why and the way in which return loss is spec'd in
various standards. In particular, in CPRI, it is required that
differentialRL < -10 dB + 10xlog(f / (625MHz)) dB for 625 MHz <= f <= [CPRI
line bit rate]

My first question is why return loss is spec'd at all. Presumably it is there
to control the magnitude of the reflections that the TX and Rx SERDES devices
impart onto the channel. On a more detailed level, why does the spec start at
625MHz? Is this related to the AC coupling cutoff frequency? And what kind of
underlying physics relate to a return loss that varies as a + b log(f/k)? This
is clearly something more nuanced than simple impedance mismatch.

I would like to know this in order to develop return loss budgets for systems
on which no spec is controlling.

Ed

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  • » [SI-LIST] Origin of Return Loss In SERDES Spec's - edward kowal