Dear Experts, In our design, we are interfacing two MDDR (Clock=133MHz, Data Rate=266MHz)in daisy-chain topology. We are using three inner layers for MDDR signal routing. Due to stackup and trace width restriction, in two layers we are maintaining the single ended impedance as 60 Ohm and in another one layer we are getting only 55 Ohms. So while switching the signal routing from one layer to another layer there will be impedance mismatch. The MDDR signal in one layer will see 60 Ohm and in another layer it will see 55 Ohm. Is it okay? or Will this impedance mismatch create any issue? Looking forward your suggestions. Thanks in Avance. Thanks and Regards MR ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu