Hi folks While designing transparent vias for a long thru path is all well and = good, keep in mind that the pseudo coax design discussed in this thread = is really an option only for a special case, of a signal via = transitioning with no stubs and return planes identical.=20 There are other, more cost effective design approaches to reduce the = impedance discontinuity and ground bounce of vias to an acceptable = level, like: - remove all NFP (non functional pads) - minimize the size of capture pads - maximize the size of antipad clearance holes - minimize the length of residual via stubs - always add at least 1 return via adjacent to a signal via - try to use the same return planes voltages for each signal layer - or at least try to match return planes between signal layers - if you can=E2=80=99t match return layers, use thin dielectric between = the different voltage planes and low L decoupling capacitors All of life's a tradeoff. You need to always evaluate the "bang for the = buck". The use of 4 return vias surrounding a signal via can not only = create a transparent via, it will also dramatically cut down on the = "ground" bounce or return bounce noise injected into the cavity of the = planes. When high isolation is needed, this via design is essential, = regardless of the residual stub.=20 As Scott McMorrow has shown, this coaxial via design, with optimized = clearance holes, can produce a nearly transparent launch of a coaxial = connector into a stripline layer of a board. He demonstrated that = contrary to popular belief, there really is a "free launch" (his = phrase).=20 This coaxial return via pattern is a very valuable design feature and = should be in every designers tool box of tricks when high isolation = between signal paths is important, like in mixed signal designs. However, implementing it for isolation control, requires all the = reference planes be the same Vss or "ground" planes. Alternatively, the = pairs of planes must match between the two transition signal layers. If = you rely on decoupling capacitors to provide the return path = connection, you defeat the purpose of minimizing the noise injected into = the cavities for ultra high isolation. Further, this via design takes up real estate in the board and routing = channels.=20 Achieving a transparent via using a signal surrounded by return vias, = even if the return planes are all identical, is really only possible = when the residual stub is very short. How short? "...it depends" The only way to answer "...it depends" questions is to "put in the = numbers." Here's how you can estimate the impact of the stubs, when the length is = short compared to the quarter wave freq (f ~ 1.5 GHz/stub len (in) ) The total capacitance in any 50 ohm transmission line in FR4 is about = 3.4 fF/mil. If you really have a 50 Ohm thru via, then this is the = excess capacitance in any stub, top or bottom. In a 40 mil long stub, = there could be about 130 fF of capacitance. This is one reason why vias = generally look capacitive, because of the stubs. Is 130 fF a lot? One way of evaluating its significance is comparing it = to the excess capacitance of a via that was designed with too low an = impedance, like 35 Ohms. The 35 ohm thru via would have about 1 fF/mil = of excess capacitance.=20 A 40 mil stub would have the same capacitive load as a thru via, = designed as 35 Ohms, that is 130 mils long. In other words, if you = design a 50 ohm via, and still have even a 40 mil total stub length, top = and bottom, this would have the same performance as if you built a = typical low impedance via that was 130 mils long.=20 Why go to all the cost of a coaxial return configuration if the = performance is the same as a typical via?- unless you needed ultra high = isolation or the coaxial configuration were free. One way of compensating for the stub capacitance is to design the via = with a higher impedance. This is tough to do, but it will decrease the = impact of the stub. That's why it's always good to remove NFPs and tweak = the other knobs to reduce the excess capacitance of vias. Unfortunately, when we are trying to eek out the last psec of = performance or the last mV of noise, it's those pesky second and third = order factors which begin to dominate and they are hard to analyze with = pencil and paper using simple approximations. That's why it is so = important for all engineers to move up the learning curve developing = expertise in the use of 3D full wave solvers. There are a number of tools on the market which allow you to = "breadboard" via designs, like Agilent's Momentum, Yuri's Simbeor, = Ansoft's HFSS and CST's Microwave Studio. Alternatively, there are a number of consultants on this list that can = drive these tools and do contract designs. The other option is to find = the experts in your company that use these tools and make them your best = friend so they will help you. Sometimes, when you have the luxury of time and can plan ahead, adding = via test structures to your current board is a way of "exploring design = space" for your next generation of product- and then using TDR or VNA = techniques to analyze the structures to find the optimum via features = for acceptable performance.=20 --eric ************************************** Dr. Eric Bogatin,=20 Signal Integrity Evangelist Bogatin Enterprises, LLC Setting the Standard for Signal Integrity Training 26235 w 110th terr Olathe, KS 66061 v: 913-393-1305 f: 913-393-0929 c:913-424-4333 e:eric@xxxxxxxxxxxxxxx www.BeTheSignal.com=20 Upcoming Signal Integrity Classes Kansas City: EPSI, July 30-31, 2008 San Jose, SICT, Aug 12-13 San Jose, EPSI, BBDP, Sept 29-Oct 2 ****************************************=20 -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] = On Behalf Of bhuvana Sent: Tuesday, July 15, 2008 5:53 AM To: Tatsuji Sakurai; si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Looking for good source of information regarding = Via tuning Hi Tatsuji, As data-communication speeds increase beyond 3 Gbps, signal integrity=20 becomes crucial for successful data transmission. Board designers try to = eliminate every impedance mismatch along the high-speed signal path, = because=20 those discontinuities generate jitter and decrease the data eye = opening=C3=A2=E2=82=AC=E2=80=9Dnot=20 only reducing the maximum possible distance of data transmission, but = also=20 minimizing the margin to common jitter specifications, such as SONET=20 (synchronous optical network) or XAUI (10-Gigabit attachment-unit=20 interface). Due to the increasing signal density on pc boards, more signal layers = are=20 necessary, and transitions with layer interconnects (vias) become=20 unavoidable. In the past, vias represented a significant source of = signal=20 distortion, because their impedance is usually around 25 to = 35=C3=8E=C2=A9. This large=20 impedance discontinuity can reduce the data eye opening by as much as 3 = dB=20 and can create a significant amount of jitter depending on the data = rate. As=20 a result, board designers have either tried to avoid vias on the = high-speed=20 lines or implemented new techniques, such as counter boring or blind = vias.=20 Those methods help but add complexity and greatly increase board cost. You can eliminate the significant impedance mismatch of standard vias = with a=20 new "coaxlike" via structure. This structure places ground vias around = the=20 signal via in a special configuration. Vias designed with this technique = show an impedance discontinuity of less than 4% = (50=C3=82=C2=B12=C3=8E=C2=A9) on a TDR=20 (time-domain-reflectometry) plot and improved signal quality. This new=20 approach creates a vertical channel with a tunable impedance. Developers = created the via structure using a simple coax model with the signal wire = in=20 the center; the surrounding ground shield builds a homogeneously = distributed=20 impedance. Four ground vias, which align in a ring around the signal via = in=20 the center, replace the uniform ground shield (Figure 1). Because these=20 outer vias connect to the pc-board ground or VDD (supply), they carry a=20 charge, and a capacitance builds between each of them and the signal = via.=20 The calculated capacitances depend on the via diameters, the dielectric=20 constant, and the distance between the signal and ground via. The = clearance=20 (antipad) of the center via "touches" the outer vias so that the = capacitance=20 is homogeneous along the vertical = channel=C3=A2=E2=82=AC=E2=80=9Dpreventing a dramatic capacitance=20 increase at every power and ground plane. The ground vias on the outside = provide the path for the signal-return current and form an inductance = loop=20 between signal and ground vias. You can calculate the capacitance and inductance formed by one ground = via=20 and the signal via with simple formulas (Reference 1). For the = calculation,=20 you can assume that the two vias are essentially two wires of equal=20 diameters. D is the center-to-center distance between the signal and the = ground via, and a is the radius of the via. The inductance, L, of one = via=20 pair calculates to: The capacitance C calculates to: EQUATION 1 Because the vertical channel, mainly formed by the five vias, is=20 homogeneous, the impedance Z calculates to: Equation 1 calculates the capacitance in a standard two-wire system. The = improved via structure adds three more ground vias so that the amount of = positive charges in the signal via stays the same, but all the negative=20 charges distribute evenly among the four ground vias. Therefore, the = overall=20 capacitance of the improved via structure is about the same as that of a = two-wire system. However, the inductance of this via model is = one-quarter of=20 the inductance of a two-wire system, because four parallel inductance = loops=20 form between the signal and the four ground vias, resulting in via = impedance=20 Z: Experimenters tested this via structure using FR4 polyclad 370, Getec, = and=20 Rogers board materials on pc boards varying from 60 mils and six layers=20 thick to 130 mils and 16 layers thick. They verified the calculated via=20 impedance with TDR measurements and a 3-D field solver from CST = (Computer=20 Simulation Technology). The formulas they derived predict the impedance=20 exceptionally well (=C3=82=C2=B12=C3=8E=C2=A9), regardless of the board = thickness, because the=20 formula for the via impedance is independent of the board thickness. = Table 1=20 compares calculated impedances for a six-layer, 62-mil FR4 test board=20 (er=3D4.1) with the TDR measurement results and simulated impedance = values=20 from the Microwave Studio 3-D field solver from CST. The calculated via=20 impedances are within 2=C3=8E=C2=A9 of the measured results. A TDR plot is a good method for determining the impedance of vias or = other=20 discontinuities on a signal channel. Figure 2 shows the TDR plot = measured on=20 two almost-identical channels of the test board. The only difference is = that=20 one channel has a regular via with a diameter of 14.5 mils and an = antipad=20 (clearance) of 10 mils, and the other channel has the improved via = structure=20 with via diameters of 14.5 mils and center-to-center distances of 41 = mils.=20 The TDR plot shows that the impedance mismatch of the SMA connector is = the=20 same in both cases. The controlled-impedance via has an impedance of = about=20 52=C3=8E=C2=A9, and the impedance of the regular via is 48 to = 54=C3=8E=C2=A9. The impedance match=20 of the regular via is worse than that of the via structure. However, for = a=20 regular via, the match is good, and, according to this plot, you should=20 expect little signal distortion. One disadvantage of the TDR measurement is that the results are relative = to=20 the rise time of the equipment. It does not show the frequency response = of=20 the discontinuity for discrete frequencies. A better way to demonstrate = and=20 compare the impedance mismatch of the vias is to look at the S21 scatter = parameter on a network analyzer (Figure 3). A plot of the S21 shows how=20 specific frequencies of the signal pass through the transmission-line=20 channel and how others get reflected or attenuated. Figure 3 shows the = S21=20 plot of the two channels in the TDR measurement. They are identical, = except=20 that one channel has the via structure (green curve), and the other = channel=20 has a regular via (yellow curve). The via structure shows an exceptional = frequency response, and the first resonances are visible at about 10 = GHz.=20 The regular via, on the other hand, shows multiple reflections over the=20 entire frequency band, even though the impedance mismatch is small. = These=20 reflections cause certain frequencies of a signal to be more attenuated = than=20 others, thus further degrading the high-speed signal. On this test board (Figure 4), the distance between the SMA connectors = and=20 the via is about 1.4 in., which equates to a frequency of about 2.35 GHz = (using Equation 2) that is clearly visible in the S21 plot. Although the = frequency response of discontinuities for an asymmetrical channel may = differ=20 slightly, the channels are designed to be symmetric. The=20 signal-return-current path mainly causes the other reflections on the=20 yellow, regular-via curve. Because the regular via provides no path for the signal-return current, = the=20 current takes the least inductive path closest to the regular via. The=20 signal-return current flows through the ground vias of the SMA connector = and=20 through the ground-via structure of the adjacent channel. Because the = return=20 current takes the closest path, resonance frequencies in the S21 plot = are,=20 as you would expect, at about 5 GHz (0.7 in.) and not at 4.2 GHz (0.8 = in.).=20 Furthermore, the return current flows from the ground vias of that SMA = to=20 the far-end SMA connector (an approximately 1.6-in.-long current path),=20 causing another resonance at about 2 GHz (equations 3 and 4). You can=20 clearly observe both phenomena, which the return current causes, in the = S21=20 plot. The following equations calculate the resonance frequencies of the = channel=20 with the regular via: EQUATION 2 EQUATION 3 EQUATION 4 The first conclusion you can draw from the S21 measurement is that the=20 resonance frequency depends greatly on the location of the discontinuity = on=20 the transmission line. This statement does not imply that you should = place=20 the via close to the transmitter or connector so that the impedance = mismatch=20 appears at frequencies greater than 10 GHz. Unfortunately, in practice, = this=20 approach would work only if there were a perfect impedance match at the=20 receiver. Otherwise, a reflection would appear at the receiver, and = another=20 reflection would appear at the via closest to the transmitter. These=20 reflections result in a lengthy distance from receiver to via to = receiver,=20 which again translates to a low resonance frequency. The second S21 measurement conclusion is that the signal-return current=20 contributes a considerable amount of reflection. The S21 measurement in=20 Figure 3 shows two almost-identical channels that differ only in their=20 signal-return path and a slightly different impedance mismatch. The S21 = plot=20 shows more reflections at the absence of this close return path for the=20 regular via because the signal-return current takes the closest, least=20 inductive path available, even if it is an inch away, thereby causing=20 resonances. The signal-return current could flow through the inner-plane capacitance = of=20 adjacent power and ground planes, but that capacitance is usually so = small=20 that only high frequencies can pass. In most cases, the signal-return=20 current flows through the closest via that connects the reference layers = of=20 the signal trace. Those return-current vias can be far from the actual=20 signal via (Figure 5). To demonstrate this effect, experimenters placed = a=20 ground via approximately 100 mils from the regular via and plotted the=20 current density in a controlled-impedance via (Figure 5a) with the = current=20 density for the structure (Figure 5b). It is clear that most of the = return=20 current flows through the added ground via some distance away. This = extra=20 distance for the return current causes reflections that appear in the = S21=20 plot. The impact of broadband reflections becomes more visible when you = examine a=20 real data signal with a wide frequency spectrum, such as a PRBS=20 (pseudorandom-bit-stream) pattern. To illustrate this impact, = experimenters=20 sent a 27=C3=A2=E2=82=AC=E2=80=9C1 PRBS pattern at 3.125 Gbps through = both channels and recorded=20 the output waveforms (Figure 6). The channels are only 2.8 in. long, but = the=20 impact of the vias is clearly visible. The regular via (yellow curve)=20 attenuates multiple frequencies, resulting in a smaller data eye and a=20 slower rise time than a controlled-impedance via (green curve). Finally, the impedance mismatch should be as small as possible. Even the = smallest mismatch shows up at one discrete frequency on the S21 plot and = impact the signal quality. You can maximize the performance of=20 controlled-impedance vias by following important design parameters, such = as=20 spacing, trace widths, and pad widths. For example, the antipad, or=20 clearance size, of the signal via is critical. It must be at least the=20 difference of distance between signal and ground via, a, and the via=20 diameter, D, so that the signal-via antipad touches the ground via.=20 Otherwise, the metal on the ground, power layer, or both comes too close = to=20 the signal via and creates additional unwanted capacitance thereby = reducing=20 the via impedance to less than the calculated 50=C3=8E=C2=A9. Likewise, every via that connects a microstrip line on the top or the = bottom=20 layer with a stripline on an inner layer creates a stub. When the stub=20 length is smaller than the signal rise time, the stub is barely = noticeable.=20 If the stub length is longer, it can cause considerable signal = distortion.=20 For example, a stub of 40 mils has a run length of about 14 psec in a = system=20 with a 3.125-Gbps signal with a rise time of approximately 50 psec. In = the=20 worst case, the stub length is a quarter- wavelength of an important=20 frequency, and the stub becomes a short circuit for that frequency,=20 canceling out the original signal. The above equations assume that the diameter is the same for the signal = and=20 the ground vias. To use different diameters, you need to modify the = formula=20 for the capacitance. Designers should choose the via diameters according = to=20 the width of the connected traces. If the trace is much smaller than the = via, the transition from the 50=C3=8E=C2=A9 trace to the via pad causes = an unwanted=20 discontinuity. Designers should also consider the distance between the=20 ground vias and the connected trace. It can become an issue when the=20 separation between the ground via and the trace is smaller than the = distance=20 between the trace and the reference layer, creating additional = capacitance=20 for the trace and again dropping the trace impedance to less than = 50=C3=8E=C2=A9. On=20 the test board, for example, the distance between the signal trace and = the=20 ground vias is about 11 mils, and the trace is about 10 mils above the=20 ground-reference layer. Another important design consideration is pad size, because every via = that=20 connects to a trace requires a pad. This pad should be as small as = possible,=20 because the distance from the pad to the ground vias is smaller than the = distance from the signal via to the ground vias. A shorter distance = results,=20 due to the pads, and increases the capacitance, which reduces the = overall=20 impedance. In a typical design, four ground vias are not always available. The via=20 structure works equally well with power vias as long as the return = current=20 has a path from VDD to ground through a nearby bypass capacitor. For example, consider boards that contain this via structure inside a = BGA=20 pinout with a 1-mm grid. Because of the fixed pinout, you may connect = only=20 two outer vias to ground; you connect the other two vias to VDD. The via = structure works well because you can also place SMD bypass capacitors=20 between VDD and ground inside the BGA. You can also use the via structure for differential signals. The signals = can=20 share the two outer vias, saving board space. Texas Instruments uses = this=20 method on the evaluation boards for its XAUI transceivers, which offer=20 limited space inside the BGA. For controlled-impedance vias, the size of = the=20 layer separation does not matter, because the ground vias and not the = metal=20 layers form the capacitance. Regular vias, however, depend on the=20 capacitance from the layers. Therefore, you must design them = specifically=20 for different layer stackups even if the board thickness does not = change. P.Bhuvana PCB Design Engineer Tessolve Services Pvt Ltd, Plot No.31 (P2), Electronic City Phase II Bangalore, 560 100 Tel : +91-80-4181 2626 Fax : +91-80-4120 2626 Cell: +91 9741187622 ----- Original Message -----=20 From: "Tatsuji Sakurai" <weissbierjp@xxxxxxxxxxx> To: <si-list@xxxxxxxxxxxxx> Sent: Tuesday, July 15, 2008 3:31 PM Subject: [SI-LIST] Re: Looking for good source of information regarding = Via=20 tuning Hello, This article "controlled impedance vias" was looked very interesting, however I have failed at the early stage of this article. I just simply did not understand "arc-cosh (D/2a)" where D is diameter of via, 2 is via pitch between sig via and GND via. If I apply typical design rule to this formula, D/2a would be value less than 1. To make this number more than 1, the design would be unlikely, I think. How do I understand this formula? Or imaginary number would be accepted in the arccosh? Can somebody explain? - Tatsuji -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of todd t Sent: Thursday, July 03, 2008 8:21 AM To: Denomme, Paul S. Cc: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: Looking for good source of information regarding Via tuning Paul, perhaps this article is of interest to you: http://www.edn.com/index.asp?layout=3Darticle&articleid=3DCA324403 "designing controlled impedance vias", by tommy neu, TI. not a replacement for a tried and true simulation study with a 3d field solver, but you'll be more familiar with what you're after and a general direction on how to get there. ciao, -todd t -mantaro networks On Jul 2, 2008, at 1:55 PM, Denomme, Paul S. wrote: > Hi All, > > > I have a customer that is looking for assistance in > providing Via tuning. Basically they are looking to minimize the > impact > their via's have on their high speed signals. I am familiar with the > various techniques to minimize the impact a via has on the signal > integrity ( ie minimize pad size, maximize anti pad, remove NFP's, > backdrilling, etc) but is their any good source of information on > how to > tune a via to a particular impedance? What about software? I'm > familiar > with the 3D field solvers, but is their any reasonably priced software > available that will support this type of work? Any assistance on this > issue would be greatly appreciated. > > > > Thank you > > > > Paul Denomme > > Viasystems > > > > > > > The information contained in this communication and its > attachment(s) is intended only for the use of the individual to whom > it is addressed and may contain information that is privileged, > confidential, or exempt from disclosure. If the reader of this > message is not the intended recipient, you are hereby notified that > any dissemination, distribution, or copying of this communication is > strictly prohibited. If you have received this communication in > error, please notify postmaster@xxxxxxxxxxxxxx and delete the > communication without retaining any copies. Thank you. > Translations of this available: > Traduction disponible chez: > Traducciones disponibles en: > Vertalingen beschikbaar bij: > http://www.viasystems.com/dynamic_page.asp?page_symbol=3Demail_footer > ____________________________________________________________________ > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > > List technical documents are available at: > http://www.si-list.net > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu > > -- =3Dtodd=3D "be who you are and say what you feel, for those who mind, don't matter, and those who matter, don't mind" --dr. seuss ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q1.gif -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q2.gif -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q3.gif -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q4.gif -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q5.gif -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q6.gif -- Binary/unsupported file stripped by Ecartis -- -- Type: image/gif -- File: 22ms927q7.gif ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: =20 //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu