[SI-LIST] Re: LC filters on SDRAM signal lines
- From: "Hany Fahmy" <hanymhfahmy@xxxxxxxxx>
- To: "'Sinha, Snehamay'" <snehamay@xxxxxx>, "'David Carney \(Neenah\)'" <David.Carney@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 25 Jun 2011 01:30:38 +0200
What about enabling spread-spectrum downstream, it may solve ur problem
without adding any parts.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Sinha, Snehamay
Sent: Saturday, June 25, 2011 1:06 AM
To: David Carney (Neenah); si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LC filters on SDRAM signal lines
David,
Adding these filters to the SDRAM data lines will most likely cause
problems to your SDRAM interface due to the extra load that the buffers have
to drive. If you are sure that the fast edges are the cause of this problem
you can add series resistors to slow down the edges and check.
regards,
Snehamay
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of David Carney (Neenah)
Sent: Friday, June 24, 2011 10:48 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] LC filters on SDRAM signal lines
I'm working on an embedded product with a GSM cellular module. The module
is picking up broadband noise in the GSM850 band (869-894 MHz) at levels of
approximately -90dBm to -100dBm from the board it is on. The noise is
causing BER levels that are too high (fails some tests). The source of the
noise has been tracked to a processor SDRAM bus interface running at 75 MHz
clock frequency. This processor and SDRAM are physically close to the GSM
module on the board. One of the many suggestions for mitigating this
problem that we are considering is to add LC filters to all of the SDRAM
data lines such as the following example parts:
Murata NFM18PS105R0J3
(http://search.murata.co.jp/Ceramy/image/img/PDF/ENG/L0111S0111NFM18PS.p
df)
TDK MEA1608PH (http://www.tdk.co.jp/tefe02/e9621_mea_signal_1.pdf)
These parts are recommended for LCD interfaces. Does anyone have experience
using these on SDRAM interfaces? Is this an effective way to solve the
problem? What considerations do we need to account for in
using them? Has anyone modeled these parts for signal integrity
simulations? We have been told by Murata that no model is available.
What modeling approach did you use?
Thanks.
David T. Carney P.E.
Senior Design Engineer
Plexus Engineering Solutions
Neenah Design Center
920.751.5646
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