[SI-LIST] Re: Key factor in SI measurement
- From: V S <for_si2003@xxxxxxxxx>
- To: 'SI LIST' <si-list@xxxxxxxxxxxxx>, Zhangkun <zhang_kun@xxxxxxxxxx>
- Date: Wed, 10 Sep 2008 05:55:41 -0700 (PDT)
Dear Zhangkun
To find the key factor you will try to answer what can make your design fail
under voltage, frequency or power supply variations. This will involve running
the margin test. There are two key margining tests. One is frequency margin
test and the other is voltage margin test. We can try to find the how much
frequency margin we have by increasing the frequency till the point it fails.
It will need some method of increasing the frequency of the bus being margined.
If there is a single clock generating all the required frequencies, we will
have to ensure that the frequencies of other sections and bus, for example, the
frequency of processor core, PCI bus etc stays unchanged. If all the
frequencies change we will not be able to know which bus or section was the
reason for the failure. The voltage margin test will involve, varying the IO
supply voltage till the bus fails. In particular case of DDR DIMMs, there can
be a number of loads DIMMs stacked. Every DIMM
is different. There is manufacturer to manufacturer variation. We should have
a method of determining, whether a DIMM in one slot continues to work under the
worst case JEDEC load condition and if so what is the voltage and frequency
margin in that case.
You can also make variation in the frequency and voltage margin while looking
for failure due to cross talk. Try to make one victim signal fail under
frequency and voltage variation while switching the signal on the adjacent data
signals.
The margining test should reveal which factor you design is more sensitive and
is likely to fail. This will be the key factor you will have to take care of.
Ideally, the set of the simulation will include single net simulation, cross
talk simulation, effect of variation in impedance, effect of load.
You can ensure your simulation is good or not using correlation experiment.
During the design stage, you should include a test points. These test points
should be very close to the receiver. In case of processor, you may use the via
with solder mask removed as your access test point. No matter how close you are
to the receiver you will likely end up about half inch or 1 inch away from the
receiver. Now take a scope shot of the signals at that point. Save it as XY
data points. Most modern oscilloscopes have capability to save scope shots as
XY data points. Now take this XY data points back to your simulation bench. In
your simulation, break up the transmission line reaching to the receiver in two
parts. The second part of the transmission line will be the length of the trace
from test point to the receiver. In the simulation try to see the signal at the
test point rather than all way to the end of the receiver. If you have the
model of the oscilloscope
probe, insert it into your simulation. Oscilloscope probes have parasitic
capacitances of the order of 0.5pf to 1 pf. Model them in your simulation.
When you have the simulation results, try to compare the measured and the
simulated signal. Align the time X-Axis and scale the Y-axis so that the two
data match. If the two signal look way too different, there is some fundamental
difference in the way you modeled the simulation components. May be the driver
model has something screwed up. May be it is the receiver model. It can also be
some syntax error. Try to rectify the things till you get something close to
the measured data.
Once you have simulation curve, that looks very similar to the measured lab
curve, you can proceed to make them as close as possible. The measured data
show a small dip near voltage peaks. May be this is because, you did not take
into account, the vias. The lab test showed overshoot which is not in your
simulation. May be you did not take into account the parasitic inductance of
the package. Include the package parasitic in the model and rerun the
simulation and correlation exercise. Measure the VCC voltage. If it is 3.37V
instead of 3.3V , make it 3.37V in the simulation too.
Continue this exercise till you get the confidence that you have simulated
everything to almost perfection.
Not everything can be correlated. For example correlating SSN noise will be
difficult. You will have a lot of capacitor already placed on the board. You
can however still run an SSN test where, you can switch all but one data line
simultaneously and look for SSN noise on the one data line. The result can have
qualitative, if not quantitative value.
--- On Tue, 9/9/08, Zhangkun <zhang_kun@xxxxxxxxxx> wrote:
> From: Zhangkun <zhang_kun@xxxxxxxxxx>
> Subject: [SI-LIST] Key factor in SI measurement
> To: "'SI LIST'" <si-list@xxxxxxxxxxxxx>
> Date: Tuesday, September 9, 2008, 7:44 PM
> Dear all:
>
> In the SI measurement, which key factor is cared?
>
> For example, in the DDR2 interface, how do you ensure SI is
> OK by means of
> measurement?
>
> I am planning a project which replace measrement by means
> of simulation.
>
> Best Regards
>
> Zhangkun
> 2008.9.10
>
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