[SI-LIST] Re: JTAG Guru's
- From: Paul Link <plink@xxxxxxxxxx>
- To: treyh123@xxxxxxxxx, Si-List <si-list@xxxxxxxxxxxxx>
- Date: Wed, 26 Sep 2001 07:36:15 -0400
Trey,
When I dealt with JTAG we used Altera devices. Altera had all of the needed
documentation for board layout. Let me try to answer your questions as
well.
1.) If you are not careful with what MODE you are in with the device you
will cause problems, my advice would be to disconect the JTAG interface
before you run in normal operation.
2.) Most manufacturers should give you a state diagram for what goes on
during the JTAG testing/programming cycle. Each transition of TMS changes
the state and the devices responds differently for each mode. Companies
such as Corelis and Teradyne make very good JTAG/ IEEE 1149.1 test
interfaces that take care of these concerns.
3.) The TRESET_N pin is there as a way to get out of a test/programming
cycle. You need to do nothing with it on a normal basis. Most
manufacturers do not even support this pin as it is so rarely used.
4.) I have found that the TI site mentioned by Jim Antonellis is very good
at supplying the information that you need to learn more about JTAG. Visit
the Corelis web site for information that they supply about IEEE 1149.1 (the
IEEE dropped the JTAG name as it was adopted as a standard interface). Also
visit http://www.asset-intertech.com they have an online and if I remember
correctly a downloadable tutorial program.
I hope that this helps and is not too long winded.
-Paul
----- Original Message -----
From: "Trey Henderson" <treyh123@xxxxxxxxx>
To: "Si-List" <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, September 25, 2001 5:40 PM
Subject: [SI-LIST] JTAG Guru's
>
>
> I am hoping there are a few people in the group that
> know JTAG fairly well. I am currently using it now
> for flashing in a new design, but I have some
> unanswered questions.
>
> The JTAG interface is made up of 5 signals:
> TMS : Test Mode Select
> TCK : Test Clock
> TREST_N : Test Reset
> TDI : Test Data IN
> TDO : Test Data OUT
>
> These signals go into the TAP (Test Access Port) and
> allow me to do boundary scan and somehow give the part
> test instructions.
>
> Questions:
> 1. What happens if I continuously toggle the JTAG
> pins when I am not flashing the part (eg, when it is
> in 'normal' operation). Will this cause the processor
> to freak out? Will it matter for some pins but not
> others?
>
> 2. I am unsure what the TMS pin does. Do I need to
> continuously do something to this pin..or, do I just
> hold it low for testing? I've read the the TAP
> controller responds to "changing" of the TMS and TCK.
>
> 3. After power-up, before I do testing or flashing,
> do I need to hold the TRESET_N pin low.
>
> 4. Anyone have a short tutorial for JTAG?
>
> Thanks for your help,
>
> -Trey
>
>
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