[SI-LIST] Intel Signal Integrity Opportunities
- From: "jsrittenhouse" <jsrittenhouse@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 16 Dec 2004 22:04:12 -0000
Intel Signal Integrity Opportunities:
Responsibilities:
Member of Validation Platform design team responsible for designing
validation platforms for the next generation IA-32 processors and
chipsets.
- Involved in the design, analysis and simulation of high-speed bus
structures (very high speed serial and multi-drop parallel buses)
- Generating of models necessary to support these activities
- Participating in the generation of system wide interconnect design
guidelines
- Interfacing with other board designers, PCB layout designers, board
fabricators and other Intel teams to help define the physical aspects
of an interconnect topology to achieve very aggressive (up to
1600MT/sec) data bus transfer rates while maintaining appropriate
signal integrity and timing margins
Qualifications:
You must possess a Master or a Bachelor of Science degree in
Electrical Engineering with more than one year of industry
experience. Additional qualifications include:
- Experience with signal integrity and microwave transmission line
theory (both frequency and time domain)
- Experience with signal integrity analysis tools and logic design
- Lab experience related to high-speed buses and device I/O
- Knowledge and experience with highspeed processor busses and/or
Gbit serial bus signaling and protocol
Positions Available In The Following Locations:
Folsom, CA
Hillsboro, OR
Santa Clara, CA
DuPont, WA
Contact:
paulx.j.tomei@xxxxxxxxx
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