[SI-LIST] Re: IBIS MODEL QUESTION
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
- To: <Stanley.Chiu@xxxxxxxxxx>
- Date: Thu, 28 Mar 2002 15:06:53 -0500
> I have encountered some ibis model problems recently, these problems
> happend
> quiet a lot, here are some examples errors below;..
The IBIS checker compares the V/T waveform data that you provided,
against the I/V curves and the test load (R_fixture, V_fixture).
Using the I/V data and test load, it can figure out the low and high
steady-state output voltages, which it assumes should also be the
initial and final waveform voltages ... assuming that the waveform
data completely covers one edge, from steady-state before switching,
to steady-state after switching.
In your example, the differences on the [Rising Waveform] are 0.01V
and 0.09V, which may be small enough to be ignored, or maybe not.
Consider them more like warnings than errors. Certainly the 0.01V
difference can be ignored. (Anything looks big when expressed as a
percentage relative to zero!)
There's little you can do to "fix" these warnings, except to make
sure that the Waveforms begin before, and end after, the waveform is
changing.
But, are these typical loads? It looks like the 50 ohm R_fixture
loads down the outputs excessively. R_fixture should be reasonably
similar to the actual load; in your case your outputs barely switch
with that load.
As to your other question, Vmeas applies to an output, but Vih and
Vil apply to inputs, so there is no reason why Vmeas should be between
Vih and Vil. Vmeas is the voltage specified by the IC menufacturer
for measuring delays at the output pin. That is the point you use
for your delay measurement.
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