[SI-LIST] Re: HyperLynx DRC
- From: "Carrier, Patrick" <Patrick_Carrier@xxxxxxxxxx>
- To: "paul.taddonio@xxxxxxxxxxxxxx" <paul.taddonio@xxxxxxxxxxxxxx>, "pcbjack@xxxxxxxxx" <pcbjack@xxxxxxxxx>, SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Tue, 15 May 2012 20:00:39 +0000
Hi Jack-
First of all, I would strongly encourage you to speak with your local Mentor
Application Engineer on these issues. Mentor has a very good group of AEs that
answer these kinds of questions all the time, and they can give you more
details and attention.
HyperLynx DRC is a new Mentor product currently in Beta that is about to
release. HyperLynx DRC has a number of built-in design rule checks targeted at
pinpointing possible EMI issues, as well as Signal Integrity and Power
Integrity issues.
The design rule check you referenced below is the I/O Coupling DRC, which
checks for excessive coupling of high-speed traces to I/O nets. Coupling
between these two types of nets creates a risk of high-frequency noise leaving
the system through the I/O net. Most I/O signals (signals that go "outside the
box") are slower signals and do not pose as much of a radiation risk, but if
higher-frequency energy couples onto these nets they become a much larger
radiation risk.
A great example of the relevance of this rule is when testing a device in an
EMC chamber that passes until you plug the cables into it, and then it starts
failing.
In regards to the addition of trace segment lengths (D1 and D3), this is done
because every closely-coupled segment couples more high-frequency energy onto
the I/O net. You are correct that it is probably best to run a crosstalk
simulation to find the exact coupling of all sections, and we encourage our
users to use simulation data to create these rules. The beauty of HyperLynx
DRC is that it is highly customizable. You can customize the built-in rules
using several built-in parameters, or you can write your own rules for anything
you can imagine. Susceptibility is a good candidate for such a rule.
Our customers range from novices to very advanced users. The novices, who may
not know exactly what to simulate, like HyperLynx DRC because it provides a
nice comprehensive list of checks for their board. The more advanced users
like the ability to customize it to write any rule they want. A common use is
to check for EMI issues - issues that cannot be practically simulated on a
system level but that still need to be addressed, like broken return paths.
As Paul pointed out, there are many manual checks that a user will perform on a
board during a design review, and these checks can be automated using HyperLynx
DRC.
In regards to pricing, I don't think you have the correct information. We do
have many different packages for all our tools with different levels of pricing.
Please contact Mentor directly for the latest pricing information.
Thanks.
--Pat
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of N. Paul Taddonio
Sent: Tuesday, May 15, 2012 12:14 PM
To: pcbjack@xxxxxxxxx; SI-LIST
Subject: [SI-LIST] Re: HyperLynx DRC
Its kind of exactly what a hardware designer does if he has no simulator yet
wants to apply some sort of crosstalk control based on rules of thumb: set a
minimum gap and then allow only a controlled amount of total coupled length. I
normally do this by eye when checking routing of PWB designs.
This seems useful to automate that process. I wonder if it can check
"tandem routes" (layer to adjacent layer).
Paul Taddonio
FuturePlus Systems
PS Jack your name is familiar did we work together in Nashua or Billerica?
----- Original Message -----
From: "Jack Olson" <pcbjack@xxxxxxxxx>
To: "SI-LIST" <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, May 15, 2012 12:33 PM
Subject: [SI-LIST] HyperLynx DRC
> I've been asked to look at a tool called HyperLynx DRC, which (I think) is
> Mentor's incorporation of the QuietExpert rules (developed in
> collaboration
> with UMR?) into the HyperLynx Tool Suite. Anyway, I thought I might share
> a
> picture that grabbed my attention as I was scanning the documentation.
> http://frontdoor.biz/PCBportal/DRC.gif
> This is just one of many types of rules that HyperLynx DRC processes, and
> for this one the user can change the default frequency and distances shown
> in the table, and Mentor will just add up the segments that cross the line
> (D1 and D3) to set the red flag.
> For one thing, it seems fishy to just add D1 and D3 together. And is
> segment D2 really "OK"? Does the default .5 inch and 40 mil settings have
> some basis at 1GHz?
> Maybe that is enough questions for one SI post, but I can't help but
> comment on the fact that the I/O line is labelled as the victim. Maybe my
> board designer bias is showing, but I tend to think of the big bad outside
> world as the aggressor, and my sensitive circuit guts as the victim (at
> least that is true for some of the sensor-based boards I design here). I
> know it works both ways for EMC certification, and it is a big job to
> CONTAIN the frequencies being used today, but can this rule be made to
> work
> both ways? I imagine that these simple rule-based DRC checks look kind of
> silly to a simulator power user, but does this type of tool have any real
> value in the circuit board development process?
> Finally, It seems curious to me that this DRC module is MUCH more
> expensive
> than the SI and PI modules. Why would that be? What is more valuable about
> a rule-checker than a simulator?
> Jack Olson
> Caterpillar, Inc.
>
>
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