[SI-LIST] Re: How to simulate length mismatch of PCB traces

Thanks for the replies.
After reviewing my problem again with Tr(rise time) around 100ps
(Er=3D4.3), 1mm~2mm line should act as a lumped capacitor based on the
formula Tr/(5*To)>length [eq.(6.32),pp239,Bakoglu]. For my case,
    100ps/(5*69ps/cm) =3D 20/69cm > length=3D1mm~2mm.
Thus I added only a lumped capacitor to one line like this.

          in1 --------------- out1 --capacitor- connected to gnd   
          in2 --------------- out2
          in3 --------------- out3
              |<----10cm---->|     |<--1mm-->|

Should I also include an inductor together with a lumped capacitor?
If the extra length I am considering were greater than 20/69cm, I
think I should follow the Ihsan's advice.
Thanks,

Yongjin

--- In si-list@xxxxxxxxxxxxxxx, "Ihsan Erdin" <erdinih@...> wrote:
>
> The question implies that the mutual coupling between the lines be
included
> otherwise the solution is trivial. If the length difference is short
> cascading a w-element is not a good solution. Indeed the w-element for
> electrically short lines should be avoided at all times. A quick and
dirty
> way is to make a ladder circuit or use a U-element (if anybody can
remember
> that...) to account for the length difference.
> Regards
> 
> Ihsan
> 
> 
> On 3/29/06, YongJin CHOI <yc2158@...> wrote:
> >
> > Dear SI members,
> > I am looking for a simple simulation method to get a
> > rough idea if one or two of the four traces is a
> > little bit longer like 1~2mm. The transmission line
> > models I am having are W-model from Hspice field
> > solver(2-D) and S-parameter model from HFSS. I can use
> > Hspice or Spectre depending on the simplicity.
> > Any comments would be appreciated.
> > Thanks,
> >
> > Yongjin CHOI
> >
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