[SI-LIST] Re: How to simulate length mismatch of PCB traces
- From: "yc2158" <yc2158@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 31 Mar 2006 15:49:26 -0000
Steve,
Thanks for pointing me out my wrong answer(don't work at midnight!!).
You are totally right.
I am considering if I have "a line with a little extra segment on the
end that the other coupled lines don't" like what you wrote.
To simplify the problem, I am not considering eR variation and don't
have meander. My simulation purpose is to see the length mismatch
effect as waveforms at each line end.
Like Ihsan mentioned, a ladder circuit seems like one solution.
But how can I decide the coupling cap/inductor values between a longer
line and the other lines? Also how can I use U element in this situation?
Thanks,
Yongjin
> >remember
--- In si-list@xxxxxxxxxxxxxxx, steve weir <weirsi@...> wrote:
>
> Yongjin, just using a C on the end of the line will distort the line
> impedance. You want to think in terms of the entire length of the
> line before representing etch as a lumped C.
>
> I think the real problem here is you need to decide what it is that
> you want/need to evaluate. Do you have a 1% effective eR variation
> line to line, some distributed meander, or do you have a line with a
> little extra segment on the end that the other coupled lines don't?
>
> Steve.
>
> At 08:51 PM 3/30/2006, yc2158 wrote:
> >Thanks for the replies.
> >After reviewing my problem again with Tr(rise time) around 100ps
> >(Er=3D3D4.3), 1mm~2mm line should act as a lumped capacitor based on the
> >formula Tr/(5*To)>length [eq.(6.32),pp239,Bakoglu]. For my case,
> > 100ps/(5*69ps/cm) =3D3D 20/69cm > length=3D3D1mm~2mm.
> >Thus I added only a lumped capacitor to one line like this.
> >
> > in1 --------------- out1 --capacitor- connected to gnd
> > in2 --------------- out2
> > in3 --------------- out3
> > |<----10cm---->| |<--1mm-->|
> >
> >Should I also include an inductor together with a lumped capacitor?
> >If the extra length I am considering were greater than 20/69cm, I
> >think I should follow the Ihsan's advice.
> >Thanks,
> >
> >Yongjin
> >
> >--- In si-list@xxxxxxxxxxxxxxx, "Ihsan Erdin" <erdinih@> wrote:
> > >
> > > The question implies that the mutual coupling between the lines be
> >included
> > > otherwise the solution is trivial. If the length difference is short
> > > cascading a w-element is not a good solution. Indeed the
w-element for
> > > electrically short lines should be avoided at all times. A quick and
> >dirty
> > > way is to make a ladder circuit or use a U-element (if anybody can
> >remember
> > > that...) to account for the length difference.
> > > Regards
> > >
> > > Ihsan
> > >
> > >
> > > On 3/29/06, YongJin CHOI <yc2158@> wrote:
> > > >
> > > > Dear SI members,
> > > > I am looking for a simple simulation method to get a
> > > > rough idea if one or two of the four traces is a
> > > > little bit longer like 1~2mm. The transmission line
> > > > models I am having are W-model from Hspice field
> > > > solver(2-D) and S-parameter model from HFSS. I can use
> > > > Hspice or Spectre depending on the simplicity.
> > > > Any comments would be appreciated.
> > > > Thanks,
> > > >
> > > > Yongjin CHOI
> > > >
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- References:
- [SI-LIST] Re: How to simulate length mismatch of PCB traces
- From: steve weir
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- » [SI-LIST] Re: How to simulate length mismatch of PCB traces
- » [SI-LIST] Re: How to simulate length mismatch of PCB traces
- » [SI-LIST] Re: How to simulate length mismatch of PCB traces
- » [SI-LIST] Re: How to simulate length mismatch of PCB traces
- » [SI-LIST] Re: How to simulate length mismatch of PCB traces
- » [SI-LIST] Re: How to simulate length mismatch of PCB traces
- [SI-LIST] Re: How to simulate length mismatch of PCB traces
- From: steve weir