[SI-LIST] Re: How to simulate ESD test of one chip CMOS chip
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: <ChrisCheng@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 7 Nov 2006 10:14:31 -0700
Doug Smith has a paper on ESD simulation that might be useful.
Perhaps you can ask him for a copy??
Best Regards
Charles Grasso
Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Pager/Short Message: 3032042974@xxxxxxxxx
Email: charles.grasso@xxxxxxxxxxxx
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Sent: Sunday, November 05, 2006 11:35 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] How to simulate ESD test of one chip CMOS chip
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Hi all,
=3D20
I have one problem. In the graph, IN+ is connected to the ground. How
can we get the energy distribution between the IN+ and IN- signal
trace when we input ESD signal into IN+. What simulation tool should I
use? Thanks.
=3D20
Best regards
Chris
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