Hello, Sorry for the slightly off-topic post, but I have not any place to ask this. In JEDEC standard for HSTL , there are speciefied the supply voltage levels: Vdd(Device supply voltage), Vddq(output supply voltage), and Vref(input reference voltage). My concerns are regarding to Vdd and Vddq. If I have a 3.3V CMOS technology, how I will deal with Vddq(which is fixed at 1.5V)? Output supply voltages is reffering at the last stage of the buffer? For that I need a different supply (1.5V)? Thank you in advance for any inputs/suggestions and patience. Regards, ROmeo ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu