[SI-LIST] HSTL standard question,


 Hello,
 Sorry for the slightly off-topic post, but I have not any place to
ask this.
 In JEDEC standard for HSTL , there are speciefied the supply voltage
levels: Vdd(Device supply voltage), Vddq(output supply voltage), and
Vref(input reference voltage).
 My concerns are regarding to Vdd and Vddq. 
If I have a 3.3V CMOS technology, how I will deal with Vddq(which is
fixed at 1.5V)? Output supply voltages is reffering at the last stage
of the buffer? For that I need a different supply (1.5V)? 
 Thank you in advance for any inputs/suggestions and patience.
Regards,
ROmeo

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