[SI-LIST] [Fwd: SATA I eye diagram]
- From: giorgio ravesio <giorgio.ravesio@xxxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Wed, 20 Apr 2005 14:13:44 +0200
Hi all,
I am doing some simulation on a SATA I bus, and I have noticed an eye
diagram violation when the lenght of the differential pair traces reduce
down to 2 inches.
The violation is a "glitch" in both the logical level (i.e the logical
higt state is affected by a glith who violate the Vih(min) while the
logical low state is affected by a glitch who violate the Vil(max).
This strange glitch is approximately 100pS long and occurs
approximately 2*Tpd from the leading edge, so I am pretty sure it is
caused by some improper termination.
What is surprising me, is that this violation occurs only in the first
bit of the pattern, i.e if I skip the first bit of the pattern
everything seems OK.
Could anyone tell me if there is a reason why only the first bit has
this strange behavior ?
Thanks in advance.
Giorgio
.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
