[SI-LIST] [Fwd: SATA I eye diagram]


Hi all,
I am doing some simulation on a SATA I bus, and I have noticed an eye 
diagram violation when the lenght of the differential pair traces reduce 
down to 2 inches.
The violation is a "glitch" in both the logical level (i.e the logical 
higt state is affected by a  glith who violate the Vih(min) while the 
logical low state is affected by a glitch who violate the Vil(max).
This strange glitch is approximately  100pS long and occurs 
approximately 2*Tpd from the leading edge, so I am pretty sure it is 
caused by some improper termination.
What is surprising me, is that this violation occurs only in the first 
bit of the pattern, i.e if I skip the first bit of the pattern 
everything seems OK.
Could anyone tell me if there is a reason why only the first bit has 
this strange behavior ?

Thanks in advance.
Giorgio


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