[SI-LIST] Re: Do you really ship products at BER 10e-xx ?
- From: "George Tang" <gtang@xxxxxxxx>
- To: <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 19 Apr 2005 19:46:23 -0700
Chris,
If you believe in statistical analysis, you can use the following method to
determine BER of your system. You first measure the PLL output (for
simplicity, assume DJ=0) and record the time that each rising edge and
falling edge occurs. From these timed events, you can calculate jitter.
Plot this distribution as a function of jitter and determine the standard
deviation. About 68% of the sample data is within +/- 1 standard deviation.
This means if your eye opening inside the receiver is larger than +/- 7
standard deviation of the PLL RJ, your BER is 1e-12 or better.
Alfred, please email me the papers offline, too.
Thanks,
George
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: Monday, April 18, 2005 7:36 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Do you really ship products at BER 10e-xx ?
I thought that's the reason why some specs like Sonet spec out jitter
transfer Fc to roll off way before the loop bandwidth. How do you get there
is another problem.
I will be intrested to know what parasitics in the PLL can approach the
unity gain frequency to impact the stablity. Long long time ago there were
concerns about the PD output rc time constant to the loop filter or the
discrete Z sampling pole but I don't know how they look like with internal
filters and faster sampling rate. Still, I claim you can always observe the
problem by the cold start step response and thereby going back to the
drawing board. No suprise there.
Here's what really get me started on this thread. Customer service always
want us to give an MTBF estimate for everything so as to generate a support
cost structure. I think I understand the power supply, fan fail, bad chips,
bad discrets and bad disks problem. But I never quite "get" the 10e-12 link
error rates. Like Paul says, I've seen peta bytes of disk humming for weeks
(minus the disk or real components failure not related to the link itself).
I don't want to scare myself silly for a statistical number that no one
really care but everyone put it in the book. But if you tell me that's real,
I will get phone calls from CS engineers. How does one budget CS service
calls for the BER down the road at 8G FCAL for a peta byte installation ?
Even if the BER is a million times better than 10e-12 ? My money is on
device (disk,fan,power supply etc) failures will dwarf the link failure
rate. But I can't proof that on a satistical basis.
Al, I will appreciate the papers off line also.
TIA,
Chris
-----Original Message-----
From: Alfred P. Neves [mailto:al.neves@xxxxxxxxxxx]
Sent: Monday, April 18, 2005 4:20 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Do you really ship products at BER 10e-xx ?
When we had to optimize the loop characteristics for PLL's an overriding
consideration has been the conflicting requirements of low jitter
generation (GR-253, Sonet) and jitter transfer. If you make the loop BW
large, and the loop gain high you often have poor loop stability of
phase/frequency, such that you reject intrinsic VCO noise, but have poor
jitter transfer performance. Remember that there are parasitics in the
loop and they cause peaking in the loop response, along with higher
order poles in VCO, so when the loop BW increases loop stability may
suffer. Verify that the equations are correct (they are usually fairly
lousy linearized approximations of a charge-pump sampling system)and the
loop is set correctly, we can check the loop dynamics with Spectrum
Analyzer and autocorrelation analysis often using Wavecrest instruments.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Monday, April 18, 2005 2:46 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Do you really ship products at BER 10e-xx ?
My PLL design is getting rusty so if I am mumbling nonsense please
correct me. If you are dealing with classical PLL design, the loop
filter is always a trade-off between the high pass VCO phase noise and
the low pass input phase noise. My money is always on the VCO phase
noise and I optimize it for such. Afterall, if I read Geogre's response
in the same thread, "But if you solve all these problems to the extent
that there is sufficient eye-opening inside the receiver, then you are
dealing with errors caused by the second-order effects, mainly the RJ
from TX PLL, RX PLL / CDR circuits." That's sounds like a controlled
input phase noise (good eye opening) vs. a out of control VCO phase
noise problem (you have non-zero BER). And that's why our employers pay
us peanuts to design a power distribution that ensure no "large supply
glitches" or at least some good PLLVDD filters to avoid that to happen,
right ?
As to making sure the loop filter damping factor, one can either observe
directly the VCO control voltage or monitor the VCO output frequency in
the modulation domain during a cold start to deduce the stability
factor, there is no magic about it. You either get it right or you are
back to the drawing board. There is no 10e-xx probably you are either
right or wrong. And if you are talking about these bang bang PLL's.
AFAIK, if you are operating under the slew rate limit, your hunting
jitter is bounded and is related to the metastability limit of the FF
you use. And they have the added bonus of even if the input phase noise
is large, they are limited by Jwalk which is sqrt of input jitter. I
can't argue that a 1ps rms xtalk MAY have a 100ps jitter within the life
time of the universe but it is hard to extend that to say a properly
design system is one big 10-exx distribution.
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