Sorry for my curiosity, but as far as I know, an oscillator
has at least three terminals, 1) power, 2) ground, 3) signal.
Which of those three terminals "has been placed in series..."
with the FB?
Thanks,
Arpad
===============================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tim Smith
Sent: Sunday, December 06, 2015 5:51 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Ferrite Beads
Thanks all for your responses.
There is no bead in the PDS; it has been placed in series with a
single-ended clock oscillator.
As this is for a low volume product, I get the impression that an RC filter
might be more suitable.
Regards,
Dr. Timothy Smith (Ph.D)
On Sat, Dec 5, 2015 at 7:11 PM, Cheng, Chris <chris.cheng@xxxxxxx> wrote:
May be you can clarify what I think you are talking about.
If you are referring to ferrite beads in power regulators, in particular
for input power filtering in switching buck regulators, their purpose is to
isolate the high edge rate di/dt switch noise injecting back into the input
power. Nowadays the switching buck edge can be fast enough to generate
100MHz ringing. Ferrite bead is much more effective than resistor or justplain bulk caps to absorb/contain these noise.
I have no idea what you are talking about using ferrite beads for clock
lines. Every reference clock design I came across uses ferrite bead to
control noise in the analog power supply to the clock generator. Not
directly to clock lines.
Now if I make the assumption you are referring to ferrite bead filters in
clock generator chips power supply. Let's have a little history on
application of PLL in digital system.
In the age of ECL, PLL were mostly discrete external components for clock
generations. In mid 80's, Prof. Dave Patterson and his student published
the first paper of using PLL for digital CMOS VLSI clock synchronization .
Overnight all the two and three letters companies in the business decided
to use PLL for their latest processor and ASIC clocking design.
Unfortunately, they all decided to work with the same three letter ASIC
power house at that time to implement their PLL. There was a very nasty bug
in the layout and the result was a very bad jitter problem. It sent the
entire valley into panic mode because no one could ship with that jitter
bug. Eventually my mentor Bill Gunning solved the problem and GTL was born,
it was probably the most stressful period of time in my career working with
him to tackle that problem. With this near death experience, every two and
three letter companies at that time double or triple down their PLL designs
to prevent jitter problem to happe
n again. From full frequency loop bandwidth extra pole PLL design to
internal regulators. You name it, they invented it.
It was around that time I started to investigate the relationship between
PLL jitter and its relationship with power supply noise. In particular, the
relationship between VCO accumulated jitter vs. power supply noise
frequency. I believe there are tons of paper published about these
relationship so google will be your friend to find out more. So I design
the first set of power filtering around the lower and upper bandwidth limit
for the PLL power supply to guarantee maximum allowable jitter budget. In
those days, clock speed were slow so my original design was R, C1,C2,C3
design to cover the necessary bandwidth. There was no ferrite bead. And the
three letter ASIC power house used that design as their basis for PLL power
filter design app note for their customers. I believe that was the first
set of power filtering app note for PLL design.
A few years later a new engineer came in to help us sustain the product,
he got the right idea to substitute the resistor with a ferrite bead
thinking it can protect the high speed noise better. Unfortunately he
forgot the filter design has to go low frequency to protect the lower limit
of the power noise band and when the cap value is large enough, the filter
is operating at resonance where the reactance of the filter is much, much
higher than the resistance. Worse, typical ferrite bead only guarantee
upper bound resistance (maximum value) but no lower bound. The Q becomes
greater than one (with no upper limit since there is no minimum resistance
) and the filter actually started magnifying noise instead of damping it.
It took me a long time to convince him to make the correction and a series
resistor was add back to the filter to control the Q. Unfortunately by then
he was able to convince a lot of clock generator vendors to change my
original R,C1,C2,C3 design to FB,C1,C2,
C3 and the FB,C1,C2,C3 filter design stuck. Those who were savvy enough
to do their own analysis would have probably draw to the right conclusion
and add back the series resistor. Some may not have the luxury of adding
series resistor because of high current demand to the power filter.
Nowadays with new PLL circuits and internal regulators, the protection
band can be very different from my original design and the filter
requirements can be very different.
YMMV but at least I can give you my version of the history of these PLL
power filter design and why ferrite beads are involved. They can be useful
and necessary but you have to do your own homework to understand why and
how to use them.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Tim Smith
Sent: Thursday, December 03, 2015 8:11 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Ferrite Beads
Hi all,
Now that I have your attention with the subject title, I would like to
seek your advice on an application of ferrite beads that I have not seen
covered much in either the literature or this list.
I understand that the use of ferrite beads in the PDS without
consideration to the problem (if any) that they are trying to solve is not
good engineering. I have read through much of the discussion of their
(mis)use in PDS, but I have recently started a position in a company that
uses them in multiple applications. One being in the PDS, but I will
challenge them on this.
The other is the use of ferrite beads in the clock lines of crystal
oscillators or clock ICs. I have inquired as to their purpose and was told
that they are there to "slow" the edges of the clock down, or reduce the
magnitude of higher order harmonics.
Consider the case where a 12.0 MHz oscillator is used as the primary clock
source of an MCU that then uses a PLL to increase the core clock rate to
168.0 MHz. The 12.0 MHz clock source has higher order harmonics in the
range of 200.0 MHz which are presumably reduced by the use of the bead.
What is the resulting edge rate at the MCU pins? I haven't yet looked at
the IBIS model for the processor, but I imagine that the harmonics on the
output of the PLL would exceed 168.0 MHz thereby rendering the bead in the
clock line redundant.
My question is if the beads are helping or are redundant?
Your thoughts are appreciated.
Regards,
Dr. Timothy Smith (Ph.D)
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