An rc or just a C works really well. On a transmission line that is 50 ohms
there is approximately 50ps per 1pF of rise time increase by adding just
capacitance
On Dec 6, 2015 10:00 PM, "Tim Smith" <tgsmith81@xxxxxxxxx> wrote:
On 12/6/2015 8:07 PM, Lee Ritchey wrote:
Why would one deliberately degrade a signal that way?I have inherited this design; however I imagine that it was done in an
attempt to slow the edges of the clock signal in an effort to reduce the
higher frequency components.
I recall one of your seminars Lee where you recommend to keep edges slow.
If the clock signal is to be used by a PLL internal to the MCU, is not the
best signal to deliver a sine wave?
Whilst I appreciate the intention of the previous designer, I don't believe
using a potentially resonant circuit is the correct way to go about it.
On Mon, Dec 7, 2015 at 1:41 PM, Kevin G. Rhoads <krhoads@xxxxxxxxxxxxxx>
wrote:
On 12/6/2015 8:07 PM, Lee Ritchey wrote:
Why would one deliberately degrade a signal that way?
It was stated several posts back that it was intended to control the
edge rise time by that ...
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