[SI-LIST] Re: FPGA output resistance question
- From: steve weir <weirsi@xxxxxxxxxx>
- To: paul@xxxxxxxxxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 06 Oct 2005 20:28:00 -0700
Paul, a couple of points:
1) You haven't said anything about how you intend to terminate the
bus. Bus settling time without proper termination is going to be much
longer than anything but an egregious rise time. A modest rise time is
easier to tame than a fast one. 24mA drivers are probably not your friend
here. On die termination probably is.
2) V4 can be damaged if you use a rail above 3.3V. Personally, I would
power at 3.0V nominal. VRMs are quite easily set to very accurate output
voltages with a single resistor. Additionally, you need to be concerned
about excessive overshoot violating Vccio_max. Such is life with modern
small geometry transistors.
3) If you have any doubts about timing, you need to at least start with a
spreadsheet timing budget. If you want to go at any appreciable rate, it
is time to be very careful, and probably simulate. You need to consider
what you are doing with your routing rules for crosstalk, etc..
4) The nasty thing about any form of TTL spec is that the voltage threshold
is very loose. Your timing budget will need to allow for that at the
receiver, as well as the driver loading.
5) All FPGAs, including V4s show bounce effects that IBIS models don't
currently handle. Talk to Xilinx about bounce data for the I/O standard,
and board stack-up you are interested in.
6) I really didn't see anything in your message about distances on your
bus. Distance matters.
7) The sparse chevron is an excellent improvement over V2 packaging, but it
is not a panacea. If you drive an outrageous bus design, you may be very
disappointed.
8) Either establish that you have gross margins that don't require
simulation, or simulate. Better yet, simulate.
9) Good designs begin with planning for the stack-up, routing rule
development and switching current demands on the parts. If you do those
parts right up-front, it will be a lot easier to dial-in a reliable design.
Steve.
At 07:19 PM 10/6/2005 -0700, Paul Mobbs wrote:
>Hello all,
>
>I've been lurking on here for over a year now, but have recently taken up a
>more focused study of SI issues. I've been slogging through Howard Johnson's
>"Highspeed Digital Design" and came to something that seemed to jump out at
>me. In 2.2.6.2 he gives an example of a totem pole output stage driving a
>multi-drop bus. Since I do this quite often, it seemed especially relevant.
>
>The basic relationship given is that Trc = Ro(driver) x (sum of load
>capacitances), then by multiplying that by 2.2 we get T(10-90). This value
>is then used to determine the maximum clock speed of the bus.
>
>I went through an upcoming design where I have a microprocessor, an FPGA,
>and a flash memory all sharing an address/data bus.
>
>So the cases would be:
>
>1) DSP drives FPGA + Flash
>2) FPGA drives DSP + Flash
>3) Flash drives DSP + FPGA
>
>Of all three cases I found that (2) had the worst T(10-90), but it was also
>the one with the least clearly-defined specs.
>
>The FPGA is a Virtex 4 and the signaling standard is LVTTL. According to the
>datasheet (p.7 of DS302 v1.9) it says "The selected standards are tested at
>a minimum VCCO with the respective VOL and VOH voltage levels shown." The
>problem is that they don't state a minimum VCCO for the LVTTL standard
>anywhere (I can see). In lieu of a given spec I chose to use a typical value
>of 3.3V for VCC, but I noticed that VCC could also be higher if we allowed
>for +/-5% rails... Which would give an even worse Ro. Is there any way to
>choose what VCC to use in such a situation?
>
>Another thought that came to mind was that all these manufacturers state
>their VOH at a different VCC than the other. For instance, the AMD flash is
>spec'd at VOHmin = 0.85 x VIO and VCC=VCCmin (2.7V). If I use this on the
>same board as the microprocessor, which let's say requires VCC of 3.3V+/-5%,
>using a VCC of 2.7V would be out of the question. Doesn't it make more sense
>to use a value for VCC that is within the limits of all devices in question?
>
>A particular issue with Xilinx FPGAs is that the output current is
>configurable. I notice that if I use a low value of 4mA my Ro is terrible,
>but if I use a higher value (up to 24mA is possible) it gets better. I
>assume there are other tradeoffs to increasing the drive current (ground
>bounce?) that go beyond this simplistic model, so I'm trying to steer clear
>of that... But I suppose the question is still valid: If you have the power
>budget and the means to increase the drive strength of your bus driver,
>should one do so for the simple purpose of improving timing?
>
>Sorry for such a long post... I've been trying to refrain from posting
>trivial or unrelated questions, so hopefully this fits those criteria.
>
>Thanks,
>Paul Mobbs
>Senior Design Engineer
>paul@xxxxxxxxxxxxxxxxx
>415-308-4795
>www.integralpoint.com
>Your partner in DSP hardware and IP development.
>
>
>
>
>
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