[SI-LIST] Re: FPGA List
- From: "Landrum, Chris" <chris_landrum@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 20 Oct 2004 13:45:51 -0400
When I was looking to do partial re-configuration on a past product (in
a past life), I went and contacted the Xilinx FAEs... Only problem was
that at the time, the FAEs did not know of anyone that had attempted
it...neither outside nor inside of Xilinx. =20
As Steve said, it's all about the floorplan. If I remember correctly
you must reconfigure on column boundaries. This makes floorplanning a
necessity, and may limit the usable area of the device.
The project ended up going in a different direction so it was never
attempted. Slick idea though.=20
-Chris
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Wednesday, October 20, 2004 12:48 PM
To: reanderson@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: FPGA List
There is a news list comp.arch.fpga. Xilinx has appnotes on partial=20
reconfiguration. Partial reconfig is rather tricky, and success is very
dependent on floorplanning.
Steve.
At 07:48 AM 10/20/2004 -0700, Ray Anderson wrote:
>Kedar P. Apte wrote:
>
> >Hello,
> >I am in need of some info about partial reconfiguration of Xilinx
FPGAs
> >
> >can any body tell me any mailing list or news group on which I can
get=20
> info about this
> >
> >thanks in advance
> >
> >Rgds
> >Kedar
> >
> >
>
>I 'm personally not aware of any mailing lists devoted to FPGA topics
>(though I'm sure that some probably exist somewhere. Try a Google
>search on: FPGA mailing list, you should come up with some
possibilities
>to check out), however the usenet newsgroup comp.arch.fpga is probably
>the appropriate venue for your questions regarding FPGAs.
>
>-Ray
>
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