[SI-LIST] Re: Effect of Via
- From: sunil bharadwaz <sunil_bharadwaz@xxxxxxxxx>
- To: Istvan Novak <istvan.novak@xxxxxxx>
- Date: Fri, 26 Dec 2008 09:18:50 -0800 (PST)
Hi Istavan ,
Thanks for the Reply !!
The board thickness is 0.4 mm.Four Layer, Second Layer is Gnd plane.
Plenty of Gnd Via's have been stitched around the Signal Vias.
100 Mhz clock is single ended.The other signal i'am concerned was 5 Ghz
RF Signal.
Regards
Sunil.b
--- On Thu, 12/25/08, Istvan Novak <istvan.novak@xxxxxxx> wrote:
From: Istvan Novak <istvan.novak@xxxxxxx>
Subject: [SI-LIST] Re: Effect of Via
To: "sunil bharadwaz" <sunil_bharadwaz@xxxxxxxxx>
Cc: "SI LIST" <si-list@xxxxxxxxxxxxx>
Date: Thursday, December 25, 2008, 9:46 PM
Sunil,
Without knowing more specifics about your geometry, here are a few
generic considerations:
As with most things in signal integrity, it is not the absolute values
that matter, rather values in relation to others.
In your case, the 6 mil drill is meaningless without knowing the feature
sizes around the via on the other layers.
If the middle layers are planes, you need openings to carry the via
barrel through. The ratio of via barrel to
the size of these openings is a good starting point estimate the via
performance. The overall board thickness
in relation to the number of plane layers is another key factor. Also,
if your signals are differential, the location
of the other via in the pair and the ground stitching via distance(s)
all make a difference.
Specifically, unless you have a very thin board and access to special
technology, you may not be able to get
your PCB fab house to make a plated through hole with 6 mil drill. If
you increase the drillsize, you may need
to increase also the size of the square pad on the other side. If the
pitch of square pads is fixed, you may be
better off using short escape traces leading to the vias.
Regards,
Istvan Novak
SUN Microsystems
sunil bharadwaz wrote:
> Hi ,
> I'am doing a form factor board where few signals are brought from top
layer to
> the bottom layer with thru hole Via's.On the bottom layer these
signals will
> be connected to the square pads laying on the edges of the PCB.The Via
> from the top layer directly goes to the bottom side square pad.The
PCB's
> are 4 to 6 layers.
>
> These form factor boards with sqaure pads will be soldered to another
Mother board , where you can access these signals.
>
> I have a 100 Mhz clock as one signal.I'am using via sizes of 6 mil
drill & 10 mil pads.
> Would be safe to increase the drill size & the pad size.
>
> If one of the signal is an 5.0 Ghz RF signal , is it safer to use bigger
via's.
> I have no access to EM simulator at this time..
>
> Can some one pls throw some light on this.I would also like to know the
> approx inductance & capacitance for these Via's.
>
> Thanks in Advance !!
>
> Best Regards
> Sunil.b
>
>
>
>
>
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