[SI-LIST] Design with DDR (SSTL-2) memory
- From: "Ravinder Ajmani" <ajmani@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 31 Jul 2001 10:49:14 -0700
Hello SI Gurus,
I am doing my first design with an SSTL-2 DDR memory. I will be using a
single or maximum two memory chips in point-to-point application. The
trace length is expected to be less than 2 inches. Here are my questions
regarding this design:
1) The memory vendor describes two modes for memory application: Reduced
Drive, and Impedance Match. What are the advantages and drawbacks of these
two modes, and which one is preferable.
2) For the length of interconnect, do I need both series and parallel
terminations, or can I get away with only one type. The ASIC interfacing
with the memory has its drivers designed for 50 ohms. My board space is
severely limited, and I would like to keep the number of terminations to a
minimum.
3) Which is the better simulation method. I have choice of using HyperLynx
or PSPICE. If I choose PSPICE, which is the better way of extracting
driver impedance and rise time from the IBIS model.
4) I will be getting 2.5V from a switching regulator. Can I use a
potential divider to get Vref from 2.5V, or should I use a separate linear
regulator. Again, board space is at a premium.
5) Any other relevant design issue.
All comments will be appreciated.
Regards, Ravinder
PCB Development and Design Department
IBM Corporation
Email: ajmani@xxxxxxxxxx
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Always do right. This will gratify some people and astonish the rest.
.... Mark Twain
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