[SI-LIST] Re: DDR2 SODIMM AT SPEEDS ABOVE 533Mbps
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <j.jebakumarsamuel@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 27 Jul 2007 08:24:04 -0700
Samuel,
I work in SIE for mobile platforms and my experience has been that Tin
order
to make 2 DIMM/channel work with a common ADR/CMD bus you will want to
look
at a couple things. A strong output buffer Ron of 13-15 ohms, and a low
impedance
motherboard trace of 30-40 ohms, between the controller and first
SO-DIMM
connector. These will tend to open the eye. Note that we also found
this
configuration very difficult to implement in a mobile form factor and so
we
generally provide separate ADR/CMD channels for each connector. You
might
want to consider this option as well if possible. However, the 2 DIMM/ch
can
be made to work if you have a strong driver and room to route the low
impedance
bus. Every application is different, but this
is what we found to be the case. =20
Brian Moran
MPAD-PED Group=20
Intel Corp.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of J.Jebakumar Samuel
Sent: Friday, July 27, 2007 6:20 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 SODIMM AT SPEEDS ABOVE 533Mbps
I am using a Virtex-4 FPGA in a new design. I have provided two sodimm
connectors. I am using 2T (common address and command bus)topology. I
tried simulating it with 2GB SODIMM modules from micron. The address and
command signals are not even passing the sstl valid levels when the
speed is beyond 200MHz. But below 200MHz it is operating fine. I am
planning to operate the SODIMM's at 666Mbps. In simulation we used,
SSTL18_IO, SSTL18_I_DCI_O, SSTL18_II_DCI_O buffers but the results are
the same. The routed trace length is just less than 5inches.
Thanks
Samuel
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=20
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