[SI-LIST] Re: DDR2 IMPEDANCE
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>, "tao xu" <helen.tao.xu@xxxxxxxxx>, <jory_mckinley@xxxxxxxxx>
- Date: Sun, 3 Dec 2006 20:33:08 -0800
Hi Kenny,
Without getting into too much detail, let me just say that the optimal
impedance
of the motherboard interconnect can vary based on the configuration. In
most cases its not so much about matching impedances of the drivers and
terminations. =20
Its more about trying to mitigate the impact of the discontinuities seen
in the interconnect, due to the nature of the DDR2 topologies. For
configs where
you have a controller connected to a single rank of memory, you can get
by
with avery traditional 50-60 ohm interconnect with 90-100 ohm diff
clocks and
strobes.=20
In more common 2 slot UDIMM and SO-DIMM based systems you will find that
a lower
motherboard impedacne will improve SI and timing, assuming your drivers
are optimized=20
for the lower impedacne routing. The low impedance helps minimize the
impedanne
discontinuity seen at the first DIMM connector, as the bus splits. Even
on the point to
point signals like CLK and CTRL, it reduces the discontinuity seen by
the driver
as the connection splits into the balanced Tee topology on the DIMM
modules.=20
Lower motherboard Zo also reduces the worst case high Z to low Z
mismatch seen
at the motherboard to DIMM boundary. This mismatch tends to degrade rise
times
and increase data bus skew. Its sometimes better to have some pre-bias
in the
nominal Zo in order to reduced this.
So you will fnd that in Intel design guides for these systems we often
recommend
40 ohm or lower routing on some or all signal groups, with 70-85 diff.
clocks and
strobes. To preserve routability you often need to optimize some signal
groups and
not others.=20
I would recommend simulation, and starting with a traditional impedance
bus,
then consider the lower Zo as an enabler. However, there is obviously a
tradeoff
between lower Zo routing and coupling immunity. You have to find the
right balance,
based on your stackup and routing contraints. =20
Brian P. Moran
Intel Corporation=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kenny Frohlich
Sent: Sunday, December 03, 2006 8:57 AM
To: tao xu; jory_mckinley@xxxxxxxxx
Cc: kenny_frohlich@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR2 IMPEDANCE
Hello Tao,
I'm interested in trace impedance on board.
I have always thought that the impedance of CLKs is 100 Ohms
(differential) and the impedance of other signals (DQ, DQM, DQS, Addr,
Commands) is 50 - 60 Ohms (single-ended). However, Intel, AMD, and
SDRAM vendors all specifies different impedance values so I got confused
and posed my questions. Also, I can not find any information on
impedance in DDR2 standard spec.
=20
Thanks,
Kenny
=20
tao xu <helen.tao.xu@xxxxxxxxx> wrote:
for trace impedance. it is normally 50 or 60 ohm based on my previous
experince. Clock singal sometimes has lower impedance trace than other
signal groups.
On 12/1/06, tao xu wrote:
> kenny, what kind of impedance did you ask? Buffer output impedance for
> interface or normal trace impedance on board?
>
> On 12/1/06, Jory McKinley wrote:
> > Hello Kenny,
> > Are you designing this type interface? If so then take a look at the
AMCC spec:
> > https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440EP/PPC440EP_
> > DS2002_v1_24.pdf
> >
> > There should be some board guideline information for the DDR
interface. You will have to simulate.
> >
> > Simulating an existing interface? If you can obtain a board file
then the traces (impedances) can be extracted for the interface.
> >
> > -Jory
> >
> >
> > Kenny Frohlich wrote: Hi All,
> > Can someone please tell me where I can find information on DDR2
impedances (ie. what is the impedance of CLK? Data? Address? Command?)?
> > We use PowerPC PPC440EP and on-board DDR2 SDRAMs.
> > Thank you.
> >
> > Regards,
> > Kenny
> >
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