[SI-LIST] Re: DDR question
- From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
- To: <dbostan@xxxxxxxxx>
- Date: Mon, 25 Oct 2004 19:24:27 -0700
By "3 SSTL_2 memories", I'm assuming that you mean three banks of memory
in parallel.
We have done it without the parallel terminator be we used series
termination at both ends in an embedded design for data signals and the
one series resistor on address and control signals. We found that while
the signals looked good both with and without the parallel termination,
the timing margins varied greatly from board to board because of the
greater variance in slew rate due to the wider voltage swing.
Simulating it, this increased slew rate was more pronounced over the
min/typ/max simulation waveforms. Our second turn of the board added
the parallel termination and after another round of in-depth timing and
signal analysis we found that inclusion of the parallel (end)
termination made the timing margins larger as well as more consistent.
This validated our hypothesis that we had coming out of simulation and
we are confident in the result.
This design had two banks of SSTL-2 memory- the equivalent of an
embedded dual bank DIMM. =20
-Chris
> -----Original Message-----
> From: Dan Bostan [mailto:dbostan@xxxxxxxxx]=20
> Sent: Monday, October 25, 2004 8:44 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] DDR question
>=20
>=20
> Did anybody try to use only the series resistor
> (22ohms) and NO far end termination to VTT, for a bank
> of 3 SSTL_2 memories?
> What results were observed/simulated?
> My question is valid for 9mA, 18mA and 24mA drive
> strength.
> Thanks,
> /dan
>=20
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