[SI-LIST] Re: DDR SDRAM layout considerations
- From: "Bob McNamara" <electronbob@xxxxxxxxxxxxx>
- To: khayden@xxxxxxxxxxxxxxxxxx,"si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 15 Sep 2003 11:10:47 -0700
Hi Ken,
We've done 4 or 5 DDR designs with no problems and most
of our customers haven't encountered any problems either.
But a few customers have had problems:
1) A 10- or 12- layer board with multiple "ground" planes,
but somebody didn't process the artwork properly. So all
but one of the ground planes was floating (i.e., no DC
connection to anything! and no connection to bypass caps
either!)
2) Parallel termination not implemented properly. In one
case the customer attempted to use R-packs with 6 pins
connecting to signals and just 2 pins connecting to Vtt.
In other cases no island was provided for Vtt. Either
way, this violates the assumption that Vtt is an AC
ground, making it more of a "crosstalker" than a
terminator.
3) We used Pericom PLL's in our early protos and found
that their frequency response had severe peaking. We
switched to either ICS or TI whose frequency responses
had much less peaking. (Specifically, when we tested
the Pericom PLL with a 2.5ns step change in phase at
its input, the output phase had more than 1.5ns of
overshoot followed by 0.5ns of undershoot; the ICS and
TI parts had about 0.5ns of overshoot and no undershoot.)
4) By far the most common problem has been caused by
improperly programming the settings of the memory
controller. Are you *absolutely* certain your problems
are SI related?
Good luck,
Bob
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