[SI-LIST] Re: Copper Fill
- From: "Loyer, Jeff W" <jeff.w.loyer@xxxxxxxxx>
- To: "'RayCaliendo@xxxxxxxxxx'" <RayCaliendo@xxxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Fri, 14 Jun 2002 07:15:09 -0700
This only applies to more exotic, expensive boards, but...
If you have buried microstrip, don't let the vendor put the copper
"thieving" over traces on that buried microstrip layer. It will have
substantial impact on those traces.
I.E., in the drawing below, don't let the vendor put thieving on L1 where it
is above traces on L2. This also applies to lettering done with copper.
L1: microstrip layer ---
dielectric
L2: buried microstrip ---
dielectric
L3: reference plane -----------------------------------
Also,
I was surprised to hear it suggested to put a via (or more) in every fill
square. I've never heard of doing that, and it sounds prohibitively
expensive. But perhaps there's some VERY high frequencies at which it
becomes necessary? This is an area where I'm skeptical, and would have to
see some demonstration of a board with and without vias on every fill square
before I took is as Standard Operating Procedure. Before I did that, I
think I would abandon the fill altogether and find another way to deal with
the issues that copper thieving addresses (board warpage, etching
consistency, environmental concerns, are there more?). But, just because I
haven't had to do it yet, doesn't mean I won't be doing it in the future. I
never dreamed I'd be telling my vendor to not put copper over my buried
microstrip traces...
Jeff Loyer
-----Original Message-----
From: RayCaliendo@xxxxxxxxxx [mailto:RayCaliendo@xxxxxxxxxx]
Sent: Thursday, June 13, 2002 3:20 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Copper Fill
Greetings,
Does anyone know, from theory or experience, what are the affects on
signal integrity or EMI, of putting copper fill in the open
areas of the PCB
top and/or bottom?
Regards,
Ray Caliendo
EMC
Solectron
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