[SI-LIST] Re: Convergence problems with Hspice
- From: Sivaraman Chokkalingam <SivaramanC@xxxxxxxxxxxxxxxx>
- To: "'khalida@xxxxxxxxxxx'" <khalida@xxxxxxxxxxx>,Si-List <si-list@xxxxxxxxxxxxx>
- Date: Wed, 26 Sep 2001 10:30:10 -0700
I have had similar problems with Hspice convergence. Here is a list of tips
I got from
an Avanti AE to workaround convergence problems:
Hspice dc non-convergence
~~~~~~~~~~~~~~~~~~~~~~~~~
Convergence is defined as the ability to obtain a solution to a set of
circuit equations within a given tolerance criteria (1). This short
collection of suggestions is designed to trade runtime performance and
loosen
certain tolerance bounds in the hopes of overcoming dc non-convergence. For
a
more comprehensive discussion on non-convergence, please see the hspice
manual.
1. Increase ilt1, which is the # of iterations hspice will attempt in
dc analysis before rejecting the solution, from its default of 200.
.option itl1 = 500
2. For circuits with feedback or multiple bias states (FF and latches),
it is important to provide hspice with an initial guess that is close
to the final solution. Use .nodeset to set initial voltage guesses. In
particular, focus on those nodes that are listed as non convergent in
the
output .lis file.
.nodeset v(in)=0 v(out)=3.3
3. Hspice will try various convergence algorithims as it struggles to
achieve DC convergence. Read the .lis file to see where hspice was when
the job aborted. Hspice first tries DCON = 1,2, then converge=1. If
this isn't enough, try the other two converge choices, along with
smaller gmindc values. Converge=3 is the source stepping method listed
in
"Inside Spice".
.option converge=2 gmindc=1e-12
1e-11
1e-10
1e-9
.option converge=3 gmindc=1e-12
1e-11
1e-10
1e-9
4. If certain active element nodes seem to be nonconvergent, you may
have hspice perform 2 dc bias point calculations. The first calculation
is performed with the active elements turned off. Then, this solution
is
used as the first guess for the dc solution with the elements turned on.
You may choose one or more elements to turn off, declared on element
line.
Diode n1 n2 diode_model off
Qbjt n1 n2 n3 bjt_model off
Mosfet n1 n2 n3 n4 mos_model off
5. While performing DC sweep, hspice now invokes the pseudo-tran
analysis
for difficult sweep points as well as DC bias calculation. To furthur
help DC sweep analysis, you may increase itl2, the number of iterations
hspice will take at each dc sweep point.
.option itl2 = 200
6. If increasing itl2 doesn't help dc sweep analysis, the problem most
likely lies in model discontinuities. (2) As a workaround, you may try
to
increase and offset the sweep size in an attempt to miss model problems.
Original: .dc vin 0v 3.3v .1v
Increase: .dc vin 0v 3.3v .2v
Offset: .dc vin .01v 3.31v .1v
Hope this helps! For more information on non convergence, please see
Hspice users manual, specifically the chap. on DC initilization and
Operating
Point analysis, sections Autoconverge Process and Reducing DC errors, and
also
Ron Kielkowski's "Inside Spice" for furthur discussion on this topic.
References:
(1) - Hspice user's man., Vol. 1, 1996 Meta-Software, for Hspice v96.1
(2) - "Inside Spice", Ron Kielkowski, McGraw-Hill, Inc., 1998, p. 71.
Hspice transient non-convergence, 'internal timestep too small' errors
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Convergence is defined as the ability to obtain a solution to a set of
circuit equations within a given tolerance criteria (1). This short
collection of suggestions is designed to trade runtime performance and
loosen
certain tolerance bounds in the hopes of overcoming 'internal timestep
too small' errors.
1. Increase itl4, which is the # of iterations hspice will try at one
time point, before giving up and taking a smaller time step. Default =
8.
This will likely affect runtime performance.
.option itl4 = 50
itl4 = 100
2. Loosen tolerance limits from their defaults:
.option reltol=1e-3 abstol=1e-8
reltol=5e-2 abstol=1e-7
reltol=1e-2 abstol=1e-6
3. Help the circuit by adding admittance and capacitance elements
between each node and ground:
.option gshunt=1e-12 cshunt=1e-12
gshunt=1e-11 cshunt=5e-11
gshunt=1e-10 cshunt=1e-11
gshunt=1e-9 cshunt=1e-10
(Note: this is the largest value I would recommend; increasing
g,c shunt larger will reduce simulation accuracy.)
4. Increase tstep value, to step over possible model discontinuities:
.tran tstep tstop ->
.tran (2)*tstep tstop
.tran (2.5)*tstep tstop
.tran (3)*tstep tstop
5. A toggle type option that may help certain high gain, analog
(op-amp) and/or oscillitory circuits (such as an inverter ring) during
tran analysis is changing integration methods. Note the time of the
tran error with default 'trap' method, then try 'gear'. If your
simulation gets furthur into the tran run, then stick with 'gear'.
Otherwise, disable the gear option.
.option method=gear
6. If you're still having trouble with timestep too small after trying
the above steps, you should investigate the device models used. For
CMOS,
make sure you have finite terminal capacitances and resistances.
For level 49, be sure you have the model parameters below: (these are
samples, not defaults)
.model mname nmos level=49 version=3.2
+ cj=5e-4 cjsw=1e-10 cgd0=1e-10 cgs0=1e-10 rs=1e-9 rd=1e-9
In the case of BJT device, be sure to have the following model param-
eters set: (examples, not default)
.model mname npn rb=50 rc=.4 re=1e-3
7. The last scenario I have encountered is the timestep too small error
occuring at time = 0; there are typically two reasons for this. Either
dc analysis wasn't performed, or unrealistic .ic voltages have been set,
and hspice can't converge with the given node voltages. Look for the
error differences between old and new iteration value, and try setting
the
node voltage with .nodeset statement somewhere closer to new guess. In
general, .nodeset is more appropriate than .ic.
-Shiva
-----Original Message-----
From: Khalid Ansari [mailto:khalida@xxxxxxxxxxx]
Sent: Tuesday, September 25, 2001 5:12 PM
To: Si-List
Subject: [SI-LIST] Convergence problems with Hspice
Hi,
I am trying to run some spice simulations but running into problems. What
I have is three blocks, basically, a driver, the package model for the IC
and
30 inches of trace (created using the W transmission line model). When I
run the driver by itself it looks like it is supposed to. Driver + package
model
looks good. Driver + transmission line model looks good, but when I put all
three together I run into all kinds of convergence problems. The package
models
were created using Ansoft Spicelink, the version of hspice that I am using
to run
these simulations is 2001.2. Has anybody seen similar errors trying to run
simulations which are similar to mine.
Thanks in advance,
Khalid
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