[SI-LIST] Chip level IBIS Modeling.
- From: <palaniappan.sivakumar@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 6 Oct 2004 18:06:28 +0530
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Hi Experts,
=0D
It would be of great help if any one could let me know how the Chip
level IBIS modelling is done.=0D
We would like to understand the chip level IBIS models and its
generation in detail.
=0D
As we know chip level IBIS modelling includes number of Pins and its pkg
parameters, how do we include pad pins and pkg parasitics?
=0D
Can I specify more than one pkg models available in more than one .pkg
file in to an IBIS model? if so how?
=0D
Can any one know where can I get some guidelines for Chip level IBIS
model creation.?
=0D
Any guidance would be appreciated.=0D
=0D
Thanks in Advance.
=0D
Regards,
Sivakumar
=0D
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