[SI-LIST] Re: Building a PBRS generator?
- From: steve weir <weirsp@xxxxxxxxxx>
- To: a.ingraham@xxxxxxxx, "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 16 Mar 2004 09:46:18 -0800
Andrew, those are all good points. But building logic with discrete parts
seems insane in this day in age. Xilinx and Altera I believe both offer
free web based tools for simple designs and this one surely fits that
category. To get the bit rate Steven should go parallel and then use a
serdes.
Regards,
Steve.
At 12:26 PM 3/16/2004 -0500, Ingraham, Andrew wrote:
>A few points to add....
>
>The circuit is an ordinary clocked logic circuit. The timing that must be
>met is at the "D" input of each register that makes up the shift register:
>Setup and Hold times of the data with respect to clock.
>
>The timing *between* the two XOR inputs is irrelevant. They just need to
>arrive and propagate through the XOR (and MUX if you use it) and the wiring
>and arrive (and stabilize) at the D input in time to meet the Setup (and
>Hold) time requirements with respect to the clock at that register.
>
>Hal Murray gave an excellent explanation.
>
>One thing I might add, is that you need to be cautious about a part's
>"toggle frequency" specification, but not just because it might be a typical
>spec as Hal mentions. Even if you use the guaranteed minimum toggle
>frequency (2.0 GHz in the case of this part), be careful of what that means.
>
>All it means is that the register can function at that frequency, *IF* you
>also meet the other timing requirements (i.e., input Setup and Hold times).
>
>(Or it might mean that you can toggle it that fast in the special case where
>you connect the D pin to its own Q-bar pin with nothing else in between.)
>
>The spec does not mean that it will work that fast in YOUR circuit, with
>paths between different registers, and extra logic in those paths. Proper
>functionality also depends on meeting the Setup and Hold times. Otherwise,
>you might find that the register does indeed clock at 2 GHz, but that it
>clocks in the "wrong" data, from two cycles ago ... because the data you
>wanted it to clock in = the outputs from the previous clock, hasn't arrived
>there yet! In this case (PRBS), that could cause a much shortened
>pseudo-random sequence which might not look random at all.
>
>Worse than that, is if the D input arrives at the wrong time and causes
>meta-stability. That could lead to a number of unpredictable effects.
>
>So your maximum frequency might be much lower than the spec, because of
>clock-to-out delay, XOR gate delay, MUX delay, wire delay, and the clock
>skew between the 23rd and 1st registers.
>
>When pushing these kinds of speeds, it is advisable not to use just the data
>sheet delays and assume zero wire delay, or even X ps / inch. It's best to
>simulate. On short interconnects, actual interconnect ("wire") delays do
>not follow simple formulas very well. Anyway, waveforms might not be what
>you expect.
>
>Also, whereas Hal describes worst-case timing at 25C, note that it gets even
>worse at both high and low temperatures.
>
>Although the MUX is not required, you do need some mechanism to assure that
>the LFSR doesn't start up in the all-0's state from which it never recovers
>(the PRBS's output would never change). If you didn't have the MUX, you
>could use the asynchronous Set or parallel-load inputs on the registers.
>
>Regards,
>Andy
>
>
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