[SI-LIST] Re: Current mode current stealing simulation by IBIS file

  • From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 16 Mar 2004 09:30:12 -0800

Sogo,

Sorry for the late reply.

I really cannot comment on what you observed without actually
trying it out with the models you used.  I haven't seen this
in my work, but I don't claim that I have seen it all...
Maybe we should take this off line if you would like to pursue
it further.

Thanks,

Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Sogo Hsu
Sent: Monday, March 01, 2004 2:54 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Current mode current stealing simulation by IBIS
file


[Sorry, resend]

Hi, Arpad,

Thank you for your fruitful comments. Current mode current stealing=20
is widely employed in clock gen. technology for Intel, such as=20
CK409, CK410 etc.. We performed the simulation works by using=20
SPECCTRAQuest and Hspice as well. The models are all in IBIS file=20
format in v3.2. These two famous simulation tools presented almost=20
the same results. The most interesting is the discrepancy=20
qualitatively between simulation and measurement and/or prediction=20
theoretically. Theoretically, the parallel termination resistors=20
shall be placed close to the driver as possible for current mode=20
current stealing technology and close to the end of receiver for=20
voltage mode to eliminate the reflection. However, the simulation=20
results did not indicate this trend for current mode current=20
stealing buffer. That is said, we also need to place the termination=20
resistor close to the end of receiver to get good signal integrity.=20
Obviously, this is not meeting the trend of measurement and=20
theoretical prediction. As I said in the previous message, this=20
trend can be exactly predicted if we create an equivalent buffer=20
model in spice format. We are unable to ensure the root cause of=20
this discrepancy. It may be the limitation of IBIS v3.2 as Lynne=20
said, or the solver=3DA1=3DA6s issue.  For us, we can only get the model =

from chip vendor. We hope we can make some modifications on IBIS=20
files and/or simulation set-up to obtain accurate simulation results=20
on this issue. Thanks for any Guru can share his/her experience.

Best Regards,

Sogo Hsu, Ph. D.
Simulation center/PCEG/Foxconn Electronic
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