[SI-LIST] Re: About the DDR2 Data Timing Budget Calculation
- From: "YangJeffrey" <steam189759@xxxxxxxxxxx>
- To: <james.f.peterson@xxxxxxxxxxxxx>, <weirsi@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Apr 2006 09:32:24 +0800
Jim,
May I understand your words like this: The skew that in the unknow
region(caused by Vil/Vih) have been included in the parameters in the derating
tables in the DDR2 spec. I can just use the propagation delay to calculate the
DDR2 timing margin?(of course, I have to calculate crosstalk and ISI, etc. )
But how can I deal with the read cycle? the DDR2 controller do not give the
derating tables in their spec usually.
Thanks,
Jeffrey Yang
> Subject: [SI-LIST] Re: About the DDR2 Data Timing Budget Calculation> Date:
> Wed, 19 Apr 2006 06:23:42 -0500> From: james.f.peterson@xxxxxxxxxxxxx> To:
> weirsi@xxxxxxxxxx; steam189759@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx> >
> Jeffrey,> > Your question is a fair one. Restated :"should I count it as skew
> when a> signal is in the unknown region". (do I have 200ps of added skew if
> it> takes 200ps to get through the unknown region?)=20> > It looks to me like
> in DDR2 this is covered by the setup and hold time> derating that is
> dependent on the actual slew rate your buffer. This> slew rate measurement,
> and the derating tables are in the DDR2 spec.> > Jim> Honeywell> >
> -----Original Message-----> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]> On Behalf Of steve weir> Sent:
> Wednesday, April 19, 2006 5:16 AM> To: steam189759@xxxxxxxxxxx;
> si-list@xxxxxxxxxxxxx> Subject: [SI-LIST] Re: About the DDR2 Data Timing
> Budget Calculation> > Jeffrey, waveform asymmetry at t
he transmitter is=3D20 part of the> transmitter skew budget. Asymmetric=3D20
response is part of the => receiver> budget. The=3D20 interconnect budget
needs to include all ( and=3D20 => only )> flight effects including push-out
/=3D20 pull-in due to cross talk. => Cross> talk is=3D20 labelled XTK and
budgeted at 55ps for data signal> interconnects.> > Steve.> At 01:57 AM
4/19/2006, YangJeffrey wrote:> >when I calculate the DDR2 data setup and
hold=3D20 margin, I use the=20> >formula(Write Case, have not=3D20 included
crosstalk and ISI=20> >effect):setup margin=3D20 =3D3D Tsetup_controller_output
- => Tdata_delay_max=20> >+ Tdqs_delay_min -=3D> Tsetup_receiver> >delay max
is measured to the Vih(when rise)delay=3D20 min is measured => to=20> >the
Vil(when rise) I think that the interconnect timing budget=3D20=20> >should
include the skew measured between Vil and Vih.> >But in Micron document:Micron
DDR2-533 Memory=3D20 design guide for=20> >two-DIMM unbuffered systems,=3D2
0 the DDR2 Write Budget is estimated in => > >the table=3D20 below:(You can
also download it from=3D20> >website:
http://download.micron.com/pdf/technotes/ddr2/tn_47_01.pdf)> >ELEMENT
KEW=3D20> >COMPONENT SETUP HOLD=3D20> >UNITS
Transmitter=3D20> >Total Skew at=3D20> >Transmitter 325 325 ps=3D20>
>Clock Data/Strobe PLL=3D20> >jitter 25 25 ps=3D20>
>DRAM=3D20> >device tDH/tDS 100=3D20> > 225
ps=3D20> > total=3D20> >Device 350 350 ps=3D20>
>Interconnect XTK (cross talk) -=3D20> >DQ 55 55 ps=3D20> >
XTK (cross talk) -=3D20> >DQS 40 40 ps=3D20> >
ISI -=3D20> >DQ 30 30 ps=3D20> >
ISI -=3D20> >DQS 5 5 ps=3D20> >
Input Capacitance=3D20> >Matching 25 25 ps=3D20> >REFF=3D20>
>Mismatch
10 10 ps=3D20> > Input Eye Reduction=3D20> >(VREF) 25 25
ps Path=3D20> >Matching (Board) 25 25 ps> >
Path Matching=3D20> > (Module) 10 10 ps Total=3D20> >
Interconnect Interconnect=3D20> > Skew 225 225 psTotal=3D20> >
Budget 1875/2 @ 533=3D20> > MHz 937.5 937.5 psTotal
Budget=3D20> > Consumed by Controller and DRAM Transmitter=3D20> > + DRAM +
Interconnect 925 925=3D20> > psInterconnect=3D20> > Budget=3D20> >
Total-(Transmitter + DRAM=3D20> > + Interconnect) 12.5 12.5=3D20> > ps
It seemed that the=3D20> > interconnect budget data in the table do
not=3D20 include the skew=20> >caused by Vil and Vih. If=3D20 considering the
skew caused by Vil and=20> >Vih, the=3D20 interconnect budget will be
negative.Can the=3D20 skew=20> >caused by Vil and Vih be ignored orit
has=3D20 been included in the => the> > >total interconnect=3D20 sk
ew in the table? Thanks,Jeffrey Yang=20>
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