[PCB_FORUM] Re: ref des problem while merging portions of multipl e schematics (Concept)
- From: "Davies, Charles (cdavies)" <cdavies@xxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 23 Mar 2006 09:52:24 -0500
Mark,
Your point is well taken on the issue with managing groups. One thought
comes to mind, a skill program could walk through the schematic and
collect the already used values and present them to you in list. It
could also present you with the next available value. No we haven't
written this yet. Haven't really had a significant need.
For this type of problem, we have used the design reuse (sub design)
methodology. It works quite well for us. More recent versions (15.5
and 15.5.1) have had substantial improvements, particularly in the area
of nested constraints.
Regards,
Charlie
321.727.6235
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg
Sent: Thursday, March 23, 2006 9:25 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: ref des problem while merging portions of
multipl e schematics (Concept)
Hi Mike,
We either package the modified schematic into an existing .brd (which
has the placement and routing for part of design already). Matching ref
des will keep their original placement. OR...Bring in the placement
through place.txt of only the components to
be cloned. Then clip in traces if necessary.
Charles,
As I mentioned, the GROUP property is also hard to manage. How do you
keep track of which ones were used?
We have not tried "sub-design" or "design reuse". Maybe it is time? We
have also been avoiding hierarchical schematics due to other issues.
regards,
Mark
gnieski_mike@xxxxxxx wrote:
>What if you hard located only the ref des that you are cloning
>placement on and leave the rest soft located? How are you cloning the
>placement? sub-design or design reuse?
>
>
>-----Original Message-----
>From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
>[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Salberg
>Sent: Thursday, March 23, 2006 8:53 AM
>To: Cadence User Group
>Subject: [PCB_FORUM] ref des problem while merging portions of multiple
>schematics (Concept)
>
>Hello all,
>I am wondering how you all would handle this?
>More and more, we are cloning schematic circuits from multiple previous
>designs.
>Reference designator management is a pain with Concept.
>
>1. First, we bring in the pages or portions of pages we want to steal
>from multiple previous designs.
>Now we need to verify there are NO duplicate ref des.
>2. So, we soft locate designators (because packager will fail with any
>assigned duplicates).
>3. But if we are also cloning placement of some components, then those
>designators must remain hard located.
>4. All Multi-section or multi-gate components must have a hard located
>ref des in order to package into a single ic.
>Problem:
>How do you manage reference designators for this situation?
>
>Thanks,
>Mark
>
>
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