Dan, Try increasing your HOLE_TO_SHAPE_SPACING spacing constraint value by the typical hole to pad edge spacing... From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Daniel So Sent: Tuesday, October 12, 2010 2:44 PM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: Suppressed Pads Mystery David The only way I was able to get the un-connected pads to suppress is to check on the "Dynamic unused pads suppression" and "Display padless holes" option. However the dynamic shape follows around the drill only. We want the shape to follow the pads as if they were there. So this will not do. I think I will need to file a bug with Cadence and Valor and see who will admit that it is a bug to them. If I edit the padstack to where there is no offset, I have no issue. So I know Jean is right. This should be working correctly whether the padstack has an offset or not. Daniel [cid:image002.jpg@01CB6A1E.A87F0190] From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Hutchins, David J Sent: Tuesday, October 12, 2010 12:13 PM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: Suppressed Pads Mystery Hey Dan, Have you tried using Allegro's 'Setup>Unused Pad Suppression' before generating the ODB++ data? the translator's "Unconnected Pads" optional parameters are disabled, since the unused pads are already removed... [cid:image003.png@01CB6A1E.A87F0190] From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean LOUISON Sent: Tuesday, October 12, 2010 11:53 AM To: icu-pcb-forum@xxxxxxxxxxxxx Subject: [PCB_FORUM] Re: Suppressed Pads Mystery Hi Daniel I think it is a bug cause by the offset... The only pads to which it works are the pads where the c-line passes through the middle of the oblong. (and not the drill) Regards. Jean Daniel So a écrit : Hi everybody I have a situation where on inner layers some pads are being suppressed and others are not. My intention is to have only the un-used pads suppressed. In the picture, route.jpg, you will see the routing on an inner layer. In the second row, there is routing going to three separate pads of the same component. Notice how each route enters the pads. In the pictures, pad-def1.jpg and pad-def2.jpg, it shows how the padstack is defined. The option "Allow suppression of unconnected internal pads" is checked on. The same offset for this padstack is used on all layers. The picture, outpout-param.jpg, shows the parameters used when creating the ODB++ output. The option "Suppress Unconnected Pads" is checked on. The picture, results.jpg, shows the results in Valor. The padstack in the middle is shown with its routing, but the padstacks on the ends are not shown with their routing. It only seems to translate if the routing is coming from below. I have changed the routing on the end pads to verify this. This situation occurs using rel 16.2 and rel 16.3. We are still using Valor/Enterprise release v8.21 bit still occurs with its latest translator. Any ideas? I hope all the pictures come through so that you can see the situation. Thank you Daniel ________________________________ ________________________________ ________________________________ ________________________________ ________________________________ ----------------------------------------------------------- To subscribe/unsubscribe: Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx with a subject of subscribe or unsubscribe To view the archives of this list go to //www.freelists.org/archives/icu-pcb-forum/ Problems or Questions: Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx -----------------------------------------------------------