[PCB_FORUM] Re: RE : Re: Retaining nets on free-standing vias
- From: "Musetti, Carl" <cmusetti@xxxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 3 Mar 2006 12:32:35 -0500
Yes shape should have the property and so should the pin
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Cosentino, Tony
Sent: Friday, March 03, 2006 11:55 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: RE : Re: Retaining nets on free-standing vias
Andrew,
Good train of thought - however the MAX_VIA_COUNT only applies to nets not
shapes. If they were able to add a MIN_VIA_COUNT then they would need to change
what objects the attributes could be applied to also.
Thanks
Tony Cosentino
Tekelec
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Andrew Noonan
(annoonan)
Sent: Friday, March 03, 2006 11:38 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: RE : Re: Retaining nets on free-standing vias
Seems to me that we already have a property called "MAX_VIA_COUNT".
Couldn't we have "MIN VIA COUNT" as well?
Just my $0.02
Andrew Noonan
CAE, PCB Design
SVBU
Cisco Systems, Inc.
annoonan@xxxxxxxxx
w 408-853-7785
c 650-814-3677
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Cosentino, Tony
Sent: Friday, March 03, 2006 7:58 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: RE : Re: Retaining nets on free-standing vias
Dave,
Please continue the ranting and raving - it is discussions like this that keep
people thinking and communicating.
We normally attach a Net_Physical_Property = 50A for nets that require 50 amps
and then we painfully calculate the required copper distribution and via
quantities needed to support this design at the required parameters. Linking
this conversation back to the original string; we then manually verify these
vias retain the nets we originally intended them to be associated with by
following our own internal process. Does anyone else have a way of applying the
needed rule and automatically verifying the requirements?
Thanks
Tony Cosentino
Tekelec
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Seymour
Sent: Friday, March 03, 2006 10:44 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: RE : Re: Retaining nets on free-standing vias
One more thing.
On power related circuits...
How does anyone check that there are enough vias and copper?
For example, 50A needed for a circuit.
If a via carries 1A, for this example.
How do I know I got 50 vias?
One via satisfies the netlist check.
One 8 mil track satisfies the netlist check
How does one check?
Currently Ranting and Raving,
Dave
Dave Seymour wrote:
Very carefully.
I do the hook up after the planes are set.
The only traces allowed on the dummy layer are the redundant
wires. So, visually there is not alot of clutter.
One could also set this up as a NET_PHYICAL_TYPE constraint and not
allow any other nets on this layer. Which would help a little, but
not solve all issues.
There is no automatic check.
Like I said "This is not elegant"
However, I have, in the past, had designs where stand alone vias
drop nets and had to come up with something.
dave
Jean-Charles TEYSSIER wrote:
I see one danger with this solution:
if the net (say GND) is not fully connected on regular layers but connected
with the "redundant" one, the pcb will not work.
How do you check this?
-------- Message d'origine--------
De: icu-pcb-forum-bounce@xxxxxxxxxxxxx de la part de Dave Seymour
Date: ven. 03/03/2006 16:05
À: icu-pcb-forum@xxxxxxxxxxxxx
Objet : [PCB_FORUM] Re: Retaining nets on free-standing vias
One solution which I have used, is to create a dummy routing
layer. Then pick a convenient component pin and hook the vias
and pin together with a connect line. This is space and routing
dependent. If there is routing room, use an existing layers.
This is not elegant, but it does ensure that the vias don't drop
the net. The dummy layer (if used) does not get plotted ( no gerber),
however
since the vias are typically gnd or power and the vias are supported
on another layer, this added connection is redundant.
It would be a really nice feature to be able to "lock" the net to the via.
Hope it helps,
dave
Malou wrote:
Hi
Yah I agree with you, but if the design have a lot of reinforcement
via to stitch your gnd or power plane meaning the whole board has
lot of scattered gnd via or power , think we can't just delete and
place a new one.
----- Original Message -----
From: Jaymole Varghese <mailto:jaymole@xxxxxxxxxxxx>
<mailto:jaymole@xxxxxxxxxxxx>
To: icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx> <mailto:icu-pcb-forum@xxxxxxxxxxxxx>
Sent: Friday, March 03, 2006 11:16 AM
Subject: [PCB_FORUM] Re: Retaining nets on free-standing vias
Hi
I don't understand why we have to go for complex
solutions. I think
if we just delete that via, place a new via in same place and
manually
giving the desired connectivity to the new via can solve this
problem.
----- Original Message -----
From: "Les Wong" <maveric0@xxxxxxxxxxx
<mailto:maveric0@xxxxxxxxxxx> <mailto:maveric0@xxxxxxxxxxx> >
To: <icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx> <mailto:icu-pcb-forum@xxxxxxxxxxxxx> >
Sent: Friday, March 03, 2006 2:18 AM
Subject: [PCB_FORUM] Re: Retaining nets on free-standing vias
> Gary:
> Is that Allegro 15.5 ?
> Les
>
> --- Gary MacIndoe <gary.macindoe@xxxxxxx
<mailto:gary.macindoe@xxxxxxx> <mailto:gary.macindoe@xxxxxxx> >
wrote:
>
> >
> > Hey guys/gals,
> >
> > Cadence has addressed this issue, at least to an
> > extent (when copying vias).
> > Go into Edit -> Copy, vias turned on, in the Options
> > tab, then check "Retain
> > net of vias" box. Then, you copy say a gnd via and
> > drop it down anywhere
> > not on a trace, it retains the gnd net. You can
> > move it around all you
> > want, it will still be gnd.
> >
> > Gary E. MacIndoe
> > PCB Design Engineer
> > Advanced Micro Devices
> > Longmont, Colorado
> >
> >
> > -----Original Message-----
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On
> > Behalf Of Daniel So
> > Sent: Thursday, March 02, 2006 12:05 PM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
> > Subject: [PCB_FORUM] Re: Retaining nets on
> > free-standing vias
> >
> > Linda
> >
> > I tried going to www.cdnusers.org <http://www.cdnusers.org>
<http://www.cdnusers.org> ,
registered and
> > then logged on. I went
> > to Forums -> Silicon-package-board -> Shared
> > code-Skill. There I saw
> > discussions but no skill codes. Where did I go
> > wrong?
> >
> > Daniel
> >
> > -----Original Message-----
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]
> > Sent: Thursday, March 02, 2006 10:37 AM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
> > Subject: [PCB_FORUM] Re: Retaining nets on
> > free-standing vias
> >
> > Doug,
> >
> > We have a PCB SKILL forum on the newly launched
> > Cadence user community
> > website where you can upload your skill routine for
> > all to see.
> >
> > you will need to register to post the code.
> >
> > The site is found at www.cdnusers.org
<http://www.cdnusers.org> <http://www.cdnusers.org> . You can
> > register, wait a bit for
> > your authorization code, login, then click on the
> > "Forums" tab in the
> > upper navigation bar.
> >
> >
> > Linda
> >
> > -----Original Message-----
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On
> > Behalf Of Douglas Stanley
> > Sent: Thursday, March 02, 2006 10:32 AM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
> > Subject: [PCB_FORUM] Re: Retaining nets on
> > free-standing vias
> >
> > My method doesn't really solve the problem, but it
> > makes it easy to deal
> > with. I wrote a small SKILL routine that allows you
> > to select any via
> > and change the via's net.
> >
> > I works by clicking on a via (single select, window,
> > or temp group) and
> > then clicking on any shape, pin, or cline. The via
> > then takes on the net
> > of the shape/pin/cline you selected. Works like a
> > champ. It's 30 lines
> > of code.
> >
> >
> >
> > Douglas G. Stanley
> > Broadcom Corporation
> > (949) 926-5889
> > dstanley@xxxxxxxxxxxx <mailto:dstanley@xxxxxxxxxxxx>
<mailto:dstanley@xxxxxxxxxxxx>
> >
> >
> >
> >
> >
> > -----Original Message-----
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On
> > Behalf Of
> > Michael.Catrambone@xxxxxxxxxx
<mailto:Michael.Catrambone@xxxxxxxxxx>
<mailto:Michael.Catrambone@xxxxxxxxxx>
> > Sent: Thursday, March 02, 2006 9:55 AM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
> > Subject: [PCB_FORUM] Re: Retaining nets on
> > free-standing vias
> >
> >
> > Hello,
> >
> > I deal with this all the time.. The best way I found
> > to handle it was to
> > define a small static shape on top of the via with
> > the net name attached
> > to it. This shape is defined a little larger than
> > the via geometry on
> > the top side of the PCB and whenever I move the via
> > I make sure to
> > select the shape as well.
> >
> > Kind of a pain but it gets me past the problem.
> > Maybe someone else has
> > a better way of handling this.
> >
> > Mike
> >
> >
> >
> >
> >
> > "Daniel So" <danielso@xxxxxxxxxxxxx>
<mailto:danielso@xxxxxxxxxxxxx> @freelists.org
<mailto:danielso@xxxxxxxxxxxxx%3E@freelists.org>
<mailto:danielso@xxxxxxxxxxxxx%3E@freelists.org>
> > on 03/02/2006
> > 11:43:43 AM
> >
> > Please respond to icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
> >
> > Sent by: icu-pcb-forum-bounce@xxxxxxxxxxxxx
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx>
> >
> >
> > To: <icu-pcb-forum@xxxxxxxxxxxxx
<mailto:icu-pcb-forum@xxxxxxxxxxxxx>
<mailto:icu-pcb-forum@xxxxxxxxxxxxx> >
> > cc:
> > Subject: [PCB_FORUM] Retaining nets on
> > free-standing vias
> >
> >
> > Hi Everyone
> >
> >
> >
> > Please excuse me if this is an old subject.
> >
> >
> >
> > I have thru-hole vias connected to a gnd plane on
> > the top layer. There
> > is +5v plane on the bottom side of the PCB. There
> > are no clines
> > connected to the vias so when ever I move the gnd
> > plane, the vias are
> > now associated to the +5v plane. I now have to move
> > the +5v plane before
> > moving back the gnd plane if I want to keep these
> > vias associated to
> > gnd. This is really a bad problem on a multi-layer
> > board with different
> > planes on different layers and when I have vias that
> > I want to keep
> > associated to different nets.
> >
> >
> >
> > Is there any way to keep the vias associated to the
> > original nets
> > without connecting clines to them? Cadence did not
> > have an answer.
> >
> >
> >
> > Thanks for any suggestions
> >
> > Daniel So
> >
> > email: danielso@xxxxxxxxxxxxx <mailto:danielso@xxxxxxxxxxxxx>
<mailto:danielso@xxxxxxxxxxxxx>
> >
> >
> >
> > (See attached file: C.htm)
> >
> >
> >
> >
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-----------------------------------------------------------
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
Dave.seymour@xxxxxxxxxxxx
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
Dave.seymour@xxxxxxxxxxxx
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